Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *   Author: Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cpuidle.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIM_JTAG_ID_REG		0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void __init imx7ulp_set_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	struct regmap *sim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	if (IS_ERR(sim)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		pr_warn("failed to read sim regmap!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 * bit[31:28] of JTAG_ID register defines revision as below from B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * 0001        B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 * 0010        B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	switch (revision >> 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		imx_set_soc_revision(IMX_CHIP_REVISION_2_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __init imx7ulp_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	imx7ulp_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	imx7ulp_set_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	of_platform_default_populate(NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const char *const imx7ulp_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	"fsl,imx7ulp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void __init imx7ulp_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	imx7ulp_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	.init_machine	= imx7ulp_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	.dt_compat	= imx7ulp_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	.init_late	= imx7ulp_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MACHINE_END