^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int ar8031_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Set RGMII IO voltage to 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) phy_write(dev, 0x1d, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) phy_write(dev, 0x1e, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* disable phy AR8031 SmartEEE function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) phy_write(dev, 0xd, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) phy_write(dev, 0xe, 0x805d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) phy_write(dev, 0xd, 0x4003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) val = phy_read(dev, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) val &= ~(0x1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) phy_write(dev, 0xe, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int bcm54220_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* enable RXC skew select RGMII copper mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) phy_write(dev, 0x1e, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) phy_write(dev, 0x1f, 0x7ea8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) phy_write(dev, 0x1e, 0x2f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) phy_write(dev, 0x1f, 0x71b7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_ID_AR8031 0x004dd074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_ID_BCM54220 0x600d8589
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void __init imx7d_enet_phy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (IS_BUILTIN(CONFIG_PHYLIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ar8031_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bcm54220_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __init imx7d_enet_clk_sel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void imx7d_enet_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) imx7d_enet_phy_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) imx7d_enet_clk_sel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void __init imx7d_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) imx_anatop_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) imx7d_enet_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __init imx7d_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void __init imx7d_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) imx_init_revision_from_anatop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) imx_src_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char *const imx7d_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "fsl,imx7d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "fsl,imx7s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .init_irq = imx7d_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .init_machine = imx7d_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .init_late = imx7d_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .dt_compat = imx7d_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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