Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/micrel_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cpuidle.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static void __init imx6ul_enet_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	if (!IS_ERR(gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int ksz8081_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		phy_write(dev, 0x1f, 0x8110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		phy_write(dev, 0x16, 0x201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		phy_write(dev, 0x1f, 0x8190);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		phy_write(dev, 0x16, 0x202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void __init imx6ul_enet_phy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (IS_BUILTIN(CONFIG_PHYLIB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 					   ksz8081_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline void imx6ul_enet_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	imx6ul_enet_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	imx6ul_enet_phy_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void __init imx6ul_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	of_platform_default_populate(NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	imx6ul_enet_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	imx_anatop_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	imx6ul_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void __init imx6ul_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	imx_init_revision_from_anatop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	imx_src_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	imx6_pm_ccm_init("fsl,imx6ul-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __init imx6ul_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	imx6sx_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char * const imx6ul_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	"fsl,imx6ul",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	"fsl,imx6ull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	.init_irq	= imx6ul_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	.init_machine	= imx6ul_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	.init_late	= imx6ul_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	.dt_compat	= imx6ul_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MACHINE_END