Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cpuidle.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static void __init imx6sl_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* set FEC clock from internal PLL clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	if (!IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		regmap_update_bits(gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		regmap_update_bits(gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void __init imx6sl_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* imx6sl reuses imx6q cpufreq driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		imx6sl_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	else if (IS_ENABLED(CONFIG_SOC_IMX6SLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		imx6sx_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void __init imx6sl_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	of_platform_default_populate(NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		imx6sl_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	imx_anatop_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	imx6sl_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void __init imx6sl_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	imx_gpc_check_dt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	imx_init_revision_from_anatop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	imx_init_l2cache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	imx_src_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		imx6_pm_ccm_init("fsl,imx6sl-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		imx6_pm_ccm_init("fsl,imx6sll-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char * const imx6sl_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	"fsl,imx6sl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	"fsl,imx6sll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	.l2c_aux_val 	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	.init_irq	= imx6sl_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	.init_machine	= imx6sl_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	.init_late      = imx6sl_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	.dt_compat	= imx6sl_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MACHINE_END