Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2011-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/micrel_phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "cpuidle.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static int ksz9021rn_phy_fixup(struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	if (IS_BUILTIN(CONFIG_PHYLIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		/* min rx data delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		/* max rx/tx clock delay, min rx/tx control delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	phy_write(dev, 0x0d, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	phy_write(dev, 0x0e, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	phy_write(dev, 0x0d, (1 << 14) | device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	phy_write(dev, 0x0e, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int ksz9031rn_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * min rx data delay, max rx/tx clock delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * min rx/tx control delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mmd_write_reg(dev, 2, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mmd_write_reg(dev, 2, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mmd_write_reg(dev, 2, 8, 0x003ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * as they are used for slots1-7 PERST#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void ventana_pciesw_early_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (!of_machine_is_compatible("gw,ventana"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (dev->devfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	pci_read_config_dword(dev, 0x62c, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	dw |= 0xaaa8; // GPIO1-7 outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	pci_write_config_dword(dev, 0x62c, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	pci_read_config_dword(dev, 0x644, &dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dw |= 0xfe;   // GPIO1-7 output high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	pci_write_config_dword(dev, 0x644, dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int ar8031_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* To enable AR8031 output a 125MHz clk from CLK_25M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	phy_write(dev, 0xd, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	phy_write(dev, 0xe, 0x8016);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	phy_write(dev, 0xd, 0x4007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	val = phy_read(dev, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	val &= 0xffe3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	val |= 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	phy_write(dev, 0xe, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* introduce tx clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	phy_write(dev, 0x1d, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	val = phy_read(dev, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	val |= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	phy_write(dev, 0x1e, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_ID_AR8031	0x004dd074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int ar8035_phy_fixup(struct phy_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Ar803x phy SmartEEE feature cause link status generates glitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * which cause ethernet link down/up issue, so disable SmartEEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	phy_write(dev, 0xd, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	phy_write(dev, 0xe, 0x805d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	phy_write(dev, 0xd, 0x4003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	val = phy_read(dev, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	phy_write(dev, 0xe, val & ~(1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * Enable 125MHz clock from CLK_25M on the AR8031.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * Also, introduce a tx clock delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * This is the same as is the AR8031 fixup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ar8031_phy_fixup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/*check phy power*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	val = phy_read(dev, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (val & BMCR_PDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		phy_write(dev, 0x0, val & ~BMCR_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHY_ID_AR8035 0x004dd072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void __init imx6q_enet_phy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_BUILTIN(CONFIG_PHYLIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				ksz9021rn_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				ksz9031rn_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				ar8031_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				ar8035_phy_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void __init imx6q_1588_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct clk *ptp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct clk *enet_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pr_warn("%s: failed to find fec node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ptp_clk = of_clk_get(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (IS_ERR(ptp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		pr_warn("%s: failed to get ptp clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	enet_ref = clk_get_sys(NULL, "enet_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (IS_ERR(enet_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		pr_warn("%s: failed to get enet clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		goto put_ptp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * (external OSC), and we need to clear the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	clksel = clk_is_match(ptp_clk, enet_ref) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				IMX6Q_GPR1_ENET_CLK_SEL_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!IS_ERR(gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		regmap_update_bits(gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	clk_put(enet_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) put_ptp_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	clk_put(ptp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void __init imx6q_axi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		 * Enable the cacheable attribute of VPU and IPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		 * AXI transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			IMX6Q_GPR4_VPU_RD_CACHE_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			IMX6Q_GPR4_IPU_WR_CACHE_CTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			IMX6Q_GPR4_IPU_RD_CACHE_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		/* Increase IPU read QoS priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		regmap_update_bits(gpr, IOMUXC_GPR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				(0xf << 16) | (0x7 << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		regmap_update_bits(gpr, IOMUXC_GPR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				(0xf << 16) | (0x7 << 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __init imx6q_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				imx_get_soc_revision());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	imx6q_enet_phy_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	of_platform_default_populate(NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	imx_anatop_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	imx6q_1588_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	imx6q_axi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void __init imx6q_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 * there is no point to run cpuidle on them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * It does work on imx6 Solo/DualLite starting from 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	    (cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		imx6q_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void __init imx6q_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	debug_ll_io_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	imx_scu_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void __init imx6q_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	imx_gpc_check_dt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	imx_init_revision_from_anatop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	imx_init_l2cache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	imx_src_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	imx6_pm_ccm_init("fsl,imx6q-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const imx6q_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	"fsl,imx6dl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	"fsl,imx6q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	"fsl,imx6qp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.l2c_aux_val 	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.smp		= smp_ops(imx_smp_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.map_io		= imx6q_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.init_irq	= imx6q_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.init_machine	= imx6q_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.init_late      = imx6q_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.dt_compat	= imx6q_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MACHINE_END