Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ASM_ARCH_MXC_IIM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ASM_ARCH_MXC_IIM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MXC_IIMSTAT             0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MXC_IIMSTATM            0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MXC_IIMERR              0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MXC_IIMEMASK            0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MXC_IIMFCTL             0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MXC_IIMUA               0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MXC_IIMLA               0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MXC_IIMSDAT             0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MXC_IIMPREV             0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MXC_IIMSREV             0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MXC_IIMPRG_P            0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MXC_IIMSCS0             0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MXC_IIMSCS1             0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MXC_IIMSCS2             0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXC_IIMSCS3             0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MXC_IIMFBAC0            0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MXC_IIMJAC              0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MXC_IIMHWV1             0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MXC_IIMHWV2             0x080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MXC_IIMHAB0             0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MXC_IIMHAB1             0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Definitions for i.MX27 TO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MXC_IIMMAC              0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MXC_IIMPREV_FUSE        0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MXC_IIMSREV_FUSE        0x081C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MXC_IIMSJC_CHALL_0      0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXC_IIMSJC_CHALL_7      0x083C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXC_IIMFB0UC17          0x0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXC_IIMFB0UC255         0x0BFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MXC_IIMFBAC1            0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Definitions for i.MX27 TO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXC_IIMSUID             0x0C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXC_IIMKEY0             0x0C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXC_IIMKEY20            0x0C54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXC_IIMSJC_RESP_0       0x0C58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXC_IIMSJC_RESP_7       0x0C74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXC_IIMFB1UC30          0x0C78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXC_IIMFB1UC255         0x0FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXC_IIMHWV1_WLOCK               (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MXC_IIMHWV2_WLOCK               (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* __ASM_ARCH_MXC_IIM_H__ */