^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) diag_reg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .word g_diag_reg - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .macro set_diag_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) adr r0, diag_reg_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ldr r1, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) add r1, r1, r0 @ r1 = physical &g_diag_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ldr r0, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ENTRY(v7_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ARM_BE8(setend be) @ go BE8 if entered LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) set_diag_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) b secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ENDPROC(v7_secondary_startup)