^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CKIH_CLK_FREQ 26000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CKIH_CLK_FREQ_27MHZ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CKIL_CLK_FREQ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern void __iomem *mx3_ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MXC_CCM_CCMR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MXC_CCM_PDR0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MXC_CCM_PDR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MX35_CCM_PDR2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MXC_CCM_RCSR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MX35_CCM_PDR3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MXC_CCM_MPCTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MX35_CCM_PDR4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXC_CCM_UPCTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MX35_CCM_RCSR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MXC_CCM_SRPCTL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MX35_CCM_MPCTL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MXC_CCM_COSR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MX35_CCM_PPCTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MXC_CCM_CGR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MX35_CCM_ACMR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MXC_CCM_CGR1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MX35_CCM_COSR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MXC_CCM_CGR2 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MX35_CCM_CGR0 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXC_CCM_WIMR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MX35_CCM_CGR1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXC_CCM_LDC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MX35_CCM_CGR2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXC_CCM_DCVR0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MX35_CCM_CGR3 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXC_CCM_DCVR1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXC_CCM_DCVR2 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXC_CCM_DCVR3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXC_CCM_LTR0 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXC_CCM_LTR1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXC_CCM_LTR2 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXC_CCM_LTR3 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MXC_CCM_LTBR0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MXC_CCM_LTBR1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXC_CCM_PMCR0 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MXC_CCM_PMCR1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MXC_CCM_PDR2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MXC_CCM_CCMR_WBEN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXC_CCM_CCMR_CSCS (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MXC_CCM_CCMR_PERCS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MXC_CCM_CCMR_SSI1S_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MXC_CCM_CCMR_SSI2S_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MXC_CCM_CCMR_LPM_OFFSET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MXC_CCM_CCMR_FIRS_OFFSET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MXC_CCM_CCMR_UPE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MXC_CCM_CCMR_SPE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MXC_CCM_CCMR_MDS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MXC_CCM_CCMR_SBYCS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MXC_CCM_CCMR_MPE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MXC_CCM_CCMR_PRCS_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MXC_CCM_PDR0_PER_PODF_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MXC_CCM_PDR1_USB_PODF_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Bit definitions for RCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MXC_CCM_RCSR_NF16B 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * LTR0 register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MXC_CCM_LTR0_DIV3CK_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MXC_CCM_LTR0_DNTHR_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MXC_CCM_LTR0_UPTHR_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * LTR1 register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MXC_CCM_LTR1_PNCTHR_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MXC_CCM_LTR1_UPCNT_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MXC_CCM_LTR1_DNCNT_OFFSET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MXC_CCM_LTR1_LTBRSR_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MXC_CCM_LTR1_LTBRSR 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MXC_CCM_LTR1_LTBRSH 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MXC_CCM_LTR2_WSW_OFFSET((x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MXC_CCM_LTR2_EMAC_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MXC_CCM_LTR2_EMAC_MASK 0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MXC_CCM_LTR3_WSW_OFFSET((x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MXC_CCM_PMCR0_DFSUP1 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MXC_CCM_PMCR0_DFSUP0 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DVSUP_TURBO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DVSUP_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DVSUP_MEDIUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DVSUP_LOW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MXC_CCM_PMCR0_DVSUP_OFFSET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MXC_CCM_PMCR0_UDSC 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MXC_CCM_PMCR0_UDSC_UP (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MXC_CCM_PMCR0_VSCNT_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MXC_CCM_PMCR0_DVFEV 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MXC_CCM_PMCR0_DVFIS 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MXC_CCM_PMCR0_LBMI 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MXC_CCM_PMCR0_LBFL 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MXC_CCM_PMCR0_LBCF_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MXC_CCM_PMCR0_PTVIS 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MXC_CCM_PMCR0_UPDTEN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MXC_CCM_PMCR0_FSVAIM 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MXC_CCM_PMCR0_FSVAI_OFFSET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MXC_CCM_PMCR0_DPVCR 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MXC_CCM_PMCR0_DPVV 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MXC_CCM_PMCR0_WFIM 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MXC_CCM_PMCR0_DRCE3 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MXC_CCM_PMCR0_DRCE2 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MXC_CCM_PMCR0_DRCE1 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MXC_CCM_PMCR0_DRCE0 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MXC_CCM_PMCR0_DCR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MXC_CCM_PMCR0_DVFEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MXC_CCM_PMCR0_PTVAIM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MXC_CCM_PMCR0_PTVAI_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MXC_CCM_PMCR0_DPTEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MXC_CCM_PMCR1_DVGP_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MXC_CCM_PMCR1_DVGP_MASK (0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MXC_CCM_DCVR_ULV_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MXC_CCM_DCVR_LLV_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MXC_CCM_DCVR_ELV_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MXC_CCM_COSR_CLKOSEL_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MXC_CCM_COSR_CLKOEN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * PMCR0 register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MXC_CCM_PMCR0_LBFL_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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