Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) unsigned int __mxc_cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static unsigned int imx_soc_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void mxc_set_cpu_type(unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	__mxc_cpu_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void imx_set_soc_revision(unsigned int rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	imx_soc_revision = rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int imx_get_soc_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	return imx_soc_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void imx_print_silicon_rev(const char *cpu, int srev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (srev == IMX_CHIP_REVISION_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		pr_info("CPU identified as %s, unknown revision\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		pr_info("CPU identified as %s, silicon rev %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				cpu, (srev >> 4) & 0xf, srev & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __init imx_set_aips(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * Set all MPROTx to be non-bufferable, trusted for R/W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * not forced to user-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	imx_writel(0x77777777, base + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	imx_writel(0x77777777, base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * Set all OPACRx to be non-bufferable, to not require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * supervisor privilege level for access, allow for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * write access and untrusted master access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	imx_writel(0x0, base + 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	imx_writel(0x0, base + 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	imx_writel(0x0, base + 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	imx_writel(0x0, base + 0x4C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	reg = imx_readl(base + 0x50) & 0x00FFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	imx_writel(reg, base + 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __init imx_aips_allow_unprivileged_access(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		const char *compat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	void __iomem *aips_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	for_each_compatible_node(np, NULL, compat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		aips_base_addr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		WARN_ON(!aips_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		imx_set_aips(aips_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }