Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * MX31 CPU type detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "iim.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int mx31_cpu_rev = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	u8 srev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	unsigned int rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) } mx31_cpu_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{ .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{ .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{ .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{ .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{ .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	{ .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	{ .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int mx31_read_cpu_rev(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	void __iomem *iim_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 i, srev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	iim_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	BUG_ON(!iim_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* read SREV register from IIM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	srev = imx_readl(iim_base + MXC_IIMSREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	srev &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		if (srev == mx31_cpu_type[i].srev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			imx_print_silicon_rev(mx31_cpu_type[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 						mx31_cpu_type[i].rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			return mx31_cpu_type[i].rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	return IMX_CHIP_REVISION_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int mx31_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (mx31_cpu_rev == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		mx31_cpu_rev = mx31_read_cpu_rev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	return mx31_cpu_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) EXPORT_SYMBOL(mx31_revision);