Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * i.MX27 specific CPU detection code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int mx27_cpu_rev = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int mx27_cpu_partnumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SYSCTRL_OFFSET		0x800	/* Offset from CCM base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int mx27_read_cpu_rev(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	void __iomem *ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	BUG_ON(!ccm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * now we have access to the IO registers. As we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 * the silicon revision very early we read it here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	 * avoid any further hooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	switch (val >> 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		return IMX_CHIP_REVISION_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		return IMX_CHIP_REVISION_2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		return IMX_CHIP_REVISION_2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		return IMX_CHIP_REVISION_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  *	the silicon revision of the cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  *	-EINVAL - not a mx27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int mx27_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (mx27_cpu_rev == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		mx27_cpu_rev = mx27_read_cpu_rev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (mx27_cpu_partnumber != 0x8821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	return mx27_cpu_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) EXPORT_SYMBOL(mx27_revision);