^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ASM_ARCH_MXC_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ASM_ARCH_MXC_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum mxc_cpu_pwr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct of_device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void mx31_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void mx35_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void imx21_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void imx31_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void imx35_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void mxc_init_irq(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void mx31_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void mx35_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void mxc_set_cpu_type(unsigned int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void mxc_restart(enum reboot_mode, const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void mxc_arch_reset_init(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void imx1_reset_init(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void imx_set_aips(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void imx_aips_allow_unprivileged_access(const char *compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int mxc_device_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void imx_set_soc_revision(unsigned int rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void imx_init_revision_from_anatop(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void imx6_enable_rbc(bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void imx_gpc_check_dt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void imx_gpc_set_arm_power_in_lpm(bool power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void imx25_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void imx27_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void imx5_pmu_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum mxc_cpu_pwr_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) WAIT_CLOCKED, /* wfi only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) WAIT_UNCLOCKED, /* WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) STOP_POWER_ON, /* just STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) STOP_POWER_OFF, /* STOP + SRPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum ulp_cpu_pwr_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ULP_PM_HSRUN, /* High speed run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ULP_PM_RUN, /* Run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ULP_PM_WAIT, /* Wait mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ULP_PM_STOP, /* Stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ULP_PM_VLPS, /* Very low power stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ULP_PM_VLLS, /* very low leakage stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void imx_enable_cpu(int cpu, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void imx_set_cpu_jump(int cpu, void *jump_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 imx_get_cpu_arg(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void imx_set_cpu_arg(int cpu, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void v7_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void imx_scu_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void imx_smp_prepare(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void imx_scu_map_io(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void imx_smp_prepare(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void imx_src_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void imx_gpc_pre_suspend(bool arm_power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void imx_gpc_post_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void imx_gpc_mask_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void imx_gpc_restore_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void imx_gpc_hwirq_mask(unsigned int hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void imx_gpc_hwirq_unmask(unsigned int hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void imx_anatop_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void imx_anatop_pre_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void imx_anatop_post_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void imx6_set_int_mem_clk_lpm(bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void imx6sl_set_wait_clk(bool enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int imx_mmdc_get_ddr_type(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void imx_cpu_die(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int imx_cpu_kill(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void imx53_suspend(void __iomem *ocram_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern const u32 imx53_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void imx6_suspend(void __iomem *ocram_vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline void imx53_suspend(void __iomem *ocram_vbase) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const u32 imx53_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void imx6_suspend(void __iomem *ocram_vbase) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void v7_cpu_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void imx6_pm_ccm_init(const char *ccm_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void imx6q_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void imx6dl_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void imx6sl_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void imx6sx_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void imx6ul_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void imx7ulp_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void imx51_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void imx53_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void imx51_pm_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void imx53_pm_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_NEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int mx51_neon_fixup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline int mx51_neon_fixup(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void imx_init_l2cache(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void imx_init_l2cache(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern const struct smp_operations imx_smp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern const struct smp_operations ls1021a_smp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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