^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "irq-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AVIC_INTCNTL 0x00 /* int control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AVIC_NIMASK 0x04 /* int mask reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AVIC_INTENNUM 0x08 /* int enable number reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AVIC_INTDISNUM 0x0C /* int disable number reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AVIC_INTENABLEH 0x10 /* int enable reg high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AVIC_INTENABLEL 0x14 /* int enable reg low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AVIC_INTTYPEH 0x18 /* int type reg high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AVIC_INTTYPEL 0x1C /* int type reg low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AVIC_NIVECSR 0x40 /* norm int vector/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AVIC_FIVECSR 0x44 /* fast int vector/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AVIC_INTSRCH 0x48 /* int source reg high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AVIC_INTSRCL 0x4C /* int source reg low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AVIC_INTFRCH 0x50 /* int force reg high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AVIC_INTFRCL 0x54 /* int force reg low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AVIC_NIPNDH 0x58 /* norm int pending high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AVIC_NIPNDL 0x5C /* norm int pending low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AVIC_FIPNDH 0x60 /* fast int pending high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AVIC_FIPNDL 0x64 /* fast int pending low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AVIC_NUM_IRQS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* low power interrupt mask registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MX25_CCM_LPIMR0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MX25_CCM_LPIMR1 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void __iomem *avic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __iomem *mx25_ccm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int irqt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (hwirq >= AVIC_NUM_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (hwirq < AVIC_NUM_IRQS / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) hwirq -= AVIC_NUM_IRQS / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* CONFIG_FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct mxc_extra_irq avic_extra_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .set_irq_fiq = avic_set_irq_fiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static u32 avic_saved_mask_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void avic_irq_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int idx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) imx_writel(gc->wake_active, avic_base + ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (mx25_ccm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * The interrupts which are still enabled will be used as wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * sources. Allow those interrupts in low-power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * The LPIMR registers use 0 to allow an interrupt, the AVIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * registers use 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) imx_writel(~gc->wake_active, mx25_ccm_base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void avic_irq_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int idx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (mx25_ccm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) imx_writel(0xffffffff, mx25_ccm_base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define avic_irq_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define avic_irq_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static __init void avic_init_gc(int idx, unsigned int irq_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) gc->private = &avic_extra_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) gc->wake_enabled = IRQ_MSK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ct->chip.irq_ack = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ct->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ct->chip.irq_suspend = avic_irq_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ct->chip.irq_resume = avic_irq_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ct->regs.ack = ct->regs.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 nivector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (nivector == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) handle_domain_irq(domain, nivector, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * This function initializes the AVIC hardware and disables all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * interrupts. It registers the interrupt enable and disable functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * to the kernel for each interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void __init mxc_init_irq(void __iomem *irqbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) avic_base = irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mx25_ccm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (mx25_ccm_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * By default, we mask all interrupts. We set the actual mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * before we go into low-power mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* put the AVIC into the reset value with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * all interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) imx_writel(0, avic_base + AVIC_INTCNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) imx_writel(0x1f, avic_base + AVIC_NIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) imx_writel(0, avic_base + AVIC_INTENABLEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) imx_writel(0, avic_base + AVIC_INTENABLEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* all IRQ no FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) imx_writel(0, avic_base + AVIC_INTTYPEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) imx_writel(0, avic_base + AVIC_INTTYPEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) WARN_ON(irq_base < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) np = of_find_compatible_node(NULL, NULL, "fsl,avic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WARN_ON(!domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) avic_init_gc(i, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Set default priority value (0) for all IRQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) set_handle_irq(avic_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Initialize FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) init_FIQ(FIQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) printk(KERN_INFO "MXC IRQ initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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