^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_SET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_CLR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ANADIG_REG_2P5 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ANADIG_REG_CORE 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ANADIG_ANA_MISC0 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ANADIG_DIGPROG 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ANADIG_DIGPROG_IMX6SL 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ANADIG_DIGPROG_IMX7D 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SRC_SBMR2 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct regmap *anatop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void imx_anatop_enable_weak2p5(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) regmap_read(anatop, ANADIG_ANA_MISC0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* can only be enabled when stop_mode_config is clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) reg = ANADIG_REG_2P5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) REG_SET : REG_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void imx_anatop_enable_fet_odrive(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) BM_ANADIG_REG_CORE_FET_ODRIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void imx_anatop_enable_2p5_pulldown(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void imx_anatop_disconnect_high_snvs(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void imx_anatop_pre_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) imx_anatop_enable_2p5_pulldown(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) imx_anatop_enable_weak2p5(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) imx_anatop_enable_fet_odrive(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) imx_anatop_disconnect_high_snvs(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void imx_anatop_post_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) imx_anatop_enable_2p5_pulldown(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) imx_anatop_enable_weak2p5(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) imx_anatop_enable_fet_odrive(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (cpu_is_imx6sl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) imx_anatop_disconnect_high_snvs(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __init imx_init_revision_from_anatop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device_node *np, *src_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *anatop_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 digprog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 offset = ANADIG_DIGPROG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 major_part, minor_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) anatop_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) WARN_ON(!anatop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) offset = ANADIG_DIGPROG_IMX6SL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offset = ANADIG_DIGPROG_IMX7D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) digprog = readl_relaxed(anatop_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iounmap(anatop_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * On i.MX7D digprog value match linux version format, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * it needn't map again and we can use register value directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) revision = digprog & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * MAJOR: [15:8], the major silicon revison;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * MINOR: [7: 0], the minor silicon revison;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * please refer to the i.MX RM for the detailed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * silicon revison bit define.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * format the major part and minor part to match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * linux kernel soc version format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) major_part = (digprog >> 8) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) minor_part = digprog & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) revision = ((major_part + 1) << 4) | minor_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if ((digprog >> 16) == MXC_CPU_IMX6ULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void __iomem *src_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 sbmr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) src_np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "fsl,imx6ul-src");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) src_base = of_iomap(src_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) of_node_put(src_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WARN_ON(!src_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iounmap(src_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (sbmr2 & (1 << 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) digprog &= ~(0xff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) digprog |= (MXC_CPU_IMX6ULZ << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mxc_set_cpu_type(digprog >> 16 & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) imx_set_soc_revision(revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __init imx_anatop_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (IS_ERR(anatop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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