Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013-2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2013-2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * 1 -- unreset; 0 -- reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CORE_RESET_BIT(x)		(1 << x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define NEON_RESET_BIT(x)		(1 << (x + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CORE_DEBUG_RESET_BIT(x)		(1 << (x + 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLUSTER_L2_RESET_BIT		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLUSTER_DEBUG_RESET_BIT		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * bits definition in SC_CPU_RESET_STATUS[x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * 1 -- reset status; 0 -- unreset status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CORE_RESET_STATUS(x)		(1 << x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define NEON_RESET_STATUS(x)		(1 << (x + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CORE_DEBUG_RESET_STATUS(x)	(1 << (x + 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLUSTER_L2_RESET_STATUS		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLUSTER_DEBUG_RESET_STATUS	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CORE_WFI_STATUS(x)		(1 << (x + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CORE_WFE_STATUS(x)		(1 << (x + 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CORE_DEBUG_ACK(x)		(1 << (x + 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SC_CPU_RESET_REQ(x)		(0x520 + (x << 3))	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SC_CPU_RESET_DREQ(x)		(0x524 + (x << 3))	/* unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SC_CPU_RESET_STATUS(x)		(0x1520 + (x << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define FAB_SF_MODE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define FAB_SF_INVLD			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* bits definition in FB_SF_INVLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define FB_SF_INVLD_START		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HIP04_MAX_CLUSTERS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HIP04_MAX_CPUS_PER_CLUSTER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define POLL_MSEC	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TIMEOUT_MSEC	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void __iomem *sysctrl, *fabric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static DEFINE_SPINLOCK(boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static u32 fabric_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * [0]: bootwrapper physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * [1]: bootwrapper size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * [2]: relocation address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * [3]: relocation size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static u32 hip04_boot_method[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static bool hip04_cluster_is_down(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (hip04_cpu_table[cluster][i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (!fabric)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	data = readl_relaxed(fabric + FAB_SF_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		data |= 1 << cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		data &= ~(1 << cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	writel_relaxed(data, fabric + FAB_SF_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	} while (data != readl_relaxed(fabric + FAB_SF_MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int mpidr, cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	void __iomem *sys_dreq, *sys_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mpidr = cpu_logical_map(l_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!sysctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	spin_lock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (hip04_cpu_table[cluster][cpu])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (hip04_cluster_is_down(cluster)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		data = CLUSTER_DEBUG_RESET_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		writel_relaxed(data, sys_dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			data = readl_relaxed(sys_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		} while (data & CLUSTER_DEBUG_RESET_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		hip04_set_snoop_filter(cluster, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	       CORE_DEBUG_RESET_BIT(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	writel_relaxed(data, sys_dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	} while (data == readl_relaxed(sys_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * We may fail to power up core again without this delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * It's not mentioned in document. It's found by test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	hip04_cpu_table[cluster][cpu]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	spin_unlock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void hip04_cpu_die(unsigned int l_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned int mpidr, cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bool last_man;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	mpidr = cpu_logical_map(l_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	spin_lock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	hip04_cpu_table[cluster][cpu]--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (hip04_cpu_table[cluster][cpu] == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		/* A power_up request went ahead of us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		spin_unlock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} else if (hip04_cpu_table[cluster][cpu] > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	last_man = hip04_cluster_is_down(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	spin_unlock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (last_man) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		/* Since it's Cortex A15, disable L2 prefetching. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		"mcr	p15, 1, %0, c15, c0, 3 \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		"isb	\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		"dsb	"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		: : "r" (0x400) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int hip04_cpu_kill(unsigned int l_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	unsigned int mpidr, cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	unsigned int data, tries, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	mpidr = cpu_logical_map(l_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	       cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	count = TIMEOUT_MSEC / POLL_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	spin_lock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	for (tries = 0; tries < count; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (hip04_cpu_table[cluster][cpu])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (data & CORE_WFI_STATUS(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		spin_unlock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* Wait for clean L2 when the whole cluster is down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		msleep(POLL_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		spin_lock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (tries >= count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	       CORE_DEBUG_RESET_BIT(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	for (tries = 0; tries < count; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (data & CORE_RESET_STATUS(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (tries >= count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (hip04_cluster_is_down(cluster))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		hip04_set_snoop_filter(cluster, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	spin_unlock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	spin_unlock_irq(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct smp_operations hip04_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.smp_boot_secondary	= hip04_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.cpu_die		= hip04_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.cpu_kill		= hip04_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static bool __init hip04_cpu_table_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int mpidr, cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mpidr = read_cpuid_mpidr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (cluster >= HIP04_MAX_CLUSTERS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	    cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		pr_err("%s: boot CPU is out of bound!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	hip04_set_snoop_filter(cluster, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	hip04_cpu_table[cluster][cpu] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int __init hip04_smp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct device_node *np, *np_sctl, *np_fab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct resource fab_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	void __iomem *relocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ret = of_property_read_u32_array(np, "boot-method",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 					 &hip04_boot_method[0], 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!np_sctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (!np_fab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!relocation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		pr_err("failed to map relocation space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		goto err_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	sysctrl = of_iomap(np_sctl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!sysctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		pr_err("failed to get sysctrl base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		goto err_sysctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ret = of_address_to_resource(np_fab, 0, &fab_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		pr_err("failed to get fabric base phys\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		goto err_fabric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	fabric_phys_addr = fab_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	sync_cache_w(&fabric_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	fabric = of_iomap(np_fab, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!fabric) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		pr_err("failed to get fabric base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		goto err_fabric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!hip04_cpu_table_init()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		goto err_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	 * Fill the instruction address that is used after secondary core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 * out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	writel_relaxed(hip04_boot_method[0], relocation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	writel_relaxed(0xa5a5a5a5, relocation + 4);	/* magic number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	writel_relaxed(__pa_symbol(secondary_startup), relocation + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	writel_relaxed(0, relocation + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	iounmap(relocation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	smp_set_ops(&hip04_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) err_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	iounmap(fabric);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err_fabric:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	iounmap(sysctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err_sysctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	iounmap(relocation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) err_reloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) early_initcall(hip04_smp_init);