Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2013 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* Sysctrl registers in Hi3620 SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SCISOEN				0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SCISODIS			0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCPERPWREN			0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCPERPWRDIS			0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCCPUCOREEN			0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCCPUCOREDIS			0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCPERCTRL0			0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCCPURSTEN			0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCCPURSTDIS			0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * bit definition in SCISOEN/SCPERPWREN/...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * CPU2_ISO_CTRL	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * CPU3_ISO_CTRL	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CPU2_ISO_CTRL			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * bit definition in SCPERCTRL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * CPU0_WFI_MASK_CFG	(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * CPU1_WFI_MASK_CFG	(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CPU0_WFI_MASK_CFG		(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * bit definition in SCCPURSTEN/...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * CPU0_SRST_REQ_EN	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * CPU1_SRST_REQ_EN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CPU0_HPM_SRST_REQ_EN		(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CPU0_DBG_SRST_REQ_EN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CPU0_NEON_SRST_REQ_EN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CPU0_SRST_REQ_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HIX5HD2_PERI_CRG20		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CRG20_CPU1_RESET		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define HIX5HD2_PERI_PMC0		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PMC0_CPU1_WAIT_MTCOMS_ACK	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PMC0_CPU1_PMC_ENABLE		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PMC0_CPU1_POWERDOWN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HIP01_PERI9                    0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PERI9_CPU1_RESET               (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	HI3620_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ERROR_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void __iomem *ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void set_cpu_hi3620(int cpu, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/* MTCMOS set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if ((cpu == 2) || (cpu == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				       ctrl_base + SCPERPWREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		/* Enable core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			| CPU0_SRST_REQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		val |= CPU0_HPM_SRST_REQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		/* ISO disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if ((cpu == 2) || (cpu == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				       ctrl_base + SCISODIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		/* WFI Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		val = readl_relaxed(ctrl_base + SCPERCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		val &= ~(CPU0_WFI_MASK_CFG << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		writel_relaxed(val, ctrl_base + SCPERCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		/* Unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		/* wfi mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		val = readl_relaxed(ctrl_base + SCPERCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		val |= (CPU0_WFI_MASK_CFG << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		writel_relaxed(val, ctrl_base + SCPERCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		/* disable core*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if ((cpu == 2) || (cpu == 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			/* iso enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				       ctrl_base + SCISOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if ((cpu == 2) || (cpu == 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			/* MTCMOS unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				       ctrl_base + SCPERPWRDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int hi3xxx_hotplug_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		id = ERROR_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ctrl_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (!ctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		id = ERROR_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	id = HI3620_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void hi3xxx_set_cpu(int cpu, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!ctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		if (hi3xxx_hotplug_init() < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (id == HI3620_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		set_cpu_hi3620(cpu, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static bool hix5hd2_hotplug_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ctrl_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void hix5hd2_set_cpu(int cpu, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		if (!hix5hd2_hotplug_init())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		/* power on cpu1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		val |= PMC0_CPU1_PMC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		/* unreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		val &= ~CRG20_CPU1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		/* power down cpu1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		val |= CRG20_CPU1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void hip01_set_cpu(int cpu, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!ctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		BUG_ON(!np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		ctrl_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		BUG_ON(!ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		/* reset on CPU1  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		temp = readl_relaxed(ctrl_base + HIP01_PERI9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		temp |= PERI9_CPU1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		writel_relaxed(temp, ctrl_base + HIP01_PERI9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		/* unreset on CPU1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		temp = readl_relaxed(ctrl_base + HIP01_PERI9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		temp &= ~PERI9_CPU1_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		writel_relaxed(temp, ctrl_base + HIP01_PERI9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline void cpu_enter_lowpower(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * Turn off coherency and L1 D-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	"	mrc	p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	"	bic	%0, %0, #0x40\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	"	mcr	p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	"	mrc	p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	"	bic	%0, %0, #0x04\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	"	mcr	p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	  : "=&r" (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	  : "r" (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	  : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void hi3xxx_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	cpu_enter_lowpower();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* We should have never returned from idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	panic("cpu %d unexpectedly exit from shutdown\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int hi3xxx_cpu_kill(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	unsigned long timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	while (hi3xxx_get_cpu_jump(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	hi3xxx_set_cpu(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void hix5hd2_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	hix5hd2_set_cpu(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #endif