Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2011 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef _MACH_HIGHBANK__SYSREGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define _MACH_HIGHBANK__SYSREGS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern void __iomem *sregs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HB_SREG_A9_PWR_REQ		0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HB_SREG_A9_BOOT_STAT		0xf04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HB_SREG_A9_BOOT_DATA		0xf08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HB_PWR_SUSPEND			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HB_PWR_SOFT_RESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HB_PWR_HARD_RESET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HB_PWR_SHUTDOWN			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SREG_CPU_PWR_CTRL(c)		(0x200 + ((c) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline void highbank_set_core_pwr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	if (scu_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline void highbank_clear_core_pwr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (scu_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void highbank_set_pwr_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	highbank_set_core_pwr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void highbank_set_pwr_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	highbank_set_core_pwr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void highbank_set_pwr_soft_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	highbank_set_core_pwr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void highbank_set_pwr_hard_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	highbank_set_core_pwr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void highbank_clear_pwr_request(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	highbank_clear_core_pwr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif