^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-footbridge/netwinder-hw.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Netwinder machine fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Russell King, Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRDA_IO_BASE 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GP1_IO_BASE 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GP2_IO_BASE 0x33a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Winbond WB83977F accessibility stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void wb977_open(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) outb(0x87, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) outb(0x87, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void wb977_close(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) outb(0xaa, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void wb977_wb(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) outb(reg, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) outb(val, 0x371);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void wb977_ww(int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) outb(reg, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) outb(val >> 8, 0x371);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) outb(reg + 1, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) outb(val & 255, 0x371);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define wb977_device_select(dev) wb977_wb(0x07, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define wb977_device_disable() wb977_wb(0x30, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define wb977_device_enable() wb977_wb(0x30, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_RAW_SPINLOCK(nw_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) EXPORT_SYMBOL(nw_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned int current_gpio_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static unsigned int current_gpio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static unsigned int current_cpld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void nw_gpio_modify_op(unsigned int mask, unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int new_gpio, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) new_gpio = (current_gpio_op & ~mask) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) changed = new_gpio ^ current_gpio_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) current_gpio_op = new_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (changed & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) outb(new_gpio, GP1_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (changed & 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) outb(new_gpio >> 8, GP2_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) EXPORT_SYMBOL(nw_gpio_modify_op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void __gpio_modify_io(int mask, int in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int new_gpio, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) new_gpio = (current_gpio_io & ~mask) | in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) changed = new_gpio ^ current_gpio_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) current_gpio_io = new_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) changed >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) new_gpio >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) wb977_device_select(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (port = 0xe1; changed && port < 0xe8; changed >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) wb977_wb(port, new_gpio & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) port += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) new_gpio >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) wb977_device_select(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (port = 0xe8; changed && port < 0xec; changed >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) wb977_wb(port, new_gpio & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) port += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) new_gpio >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void nw_gpio_modify_io(unsigned int mask, unsigned int in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Open up the SuperIO chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wb977_open();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __gpio_modify_io(mask, in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Close up the EFER gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) wb977_close();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EXPORT_SYMBOL(nw_gpio_modify_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int nw_gpio_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) EXPORT_SYMBOL(nw_gpio_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Initialise the Winbond W83977F global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void wb977_init_global(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Enable R/W config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) wb977_wb(0x26, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Power down FDC (not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) wb977_wb(0x22, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * GP12, GP11, CIRRX, IRRXH, GP10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) wb977_wb(0x2a, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * GP23, GP22, GP21, GP20, GP13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) wb977_wb(0x2b, 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * GP17, GP16, GP15, GP14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) wb977_wb(0x2c, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Initialise the Winbond W83977F printer port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void wb977_init_printer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) wb977_device_select(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * mode 1 == EPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wb977_wb(0xf0, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Initialise the Winbond W83977F keyboard controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void wb977_init_keyboard(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) wb977_device_select(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Keyboard controller address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) wb977_ww(0x60, 0x0060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) wb977_ww(0x62, 0x0064);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Keyboard IRQ 1, active high, edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) wb977_wb(0x70, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) wb977_wb(0x71, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Mouse IRQ 5, active high, edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) wb977_wb(0x72, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) wb977_wb(0x73, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * KBC 8MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) wb977_wb(0xf0, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Enable device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wb977_device_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Initialise the Winbond W83977F Infra-Red device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline void wb977_init_irda(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wb977_device_select(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * IR base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) wb977_ww(0x60, IRDA_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * IRDA IRQ 6, active high, edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wb977_wb(0x70, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) wb977_wb(0x71, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * RX DMA - ISA DMA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wb977_wb(0x74, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * TX DMA - Disable Tx DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) wb977_wb(0x75, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Append CRC, Enable bank selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) wb977_wb(0xf0, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Enable device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wb977_device_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Initialise Winbond W83977F general purpose IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static inline void wb977_init_gpio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Set up initial I/O definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) current_gpio_io = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) __gpio_modify_io(-1, GPIO_DONE | GPIO_WDTIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wb977_device_select(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Group1 base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wb977_ww(0x60, GP1_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wb977_ww(0x62, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) wb977_ww(0x64, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * GP10 (Orage button) IRQ 10, active high, edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) wb977_wb(0x70, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) wb977_wb(0x71, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * GP10: Debounce filter enabled, IRQ, input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wb977_wb(0xe0, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Enable Group1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) wb977_device_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) wb977_device_select(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Group2 base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) wb977_ww(0x60, GP2_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Clear watchdog timer regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * - timer disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) wb977_wb(0xf2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * - disable LED, no mouse nor keyboard IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) wb977_wb(0xf3, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * - timer counting, disable power LED, disable timeouot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) wb977_wb(0xf4, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Enable group2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) wb977_device_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Set Group1/Group2 outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) raw_spin_lock_irqsave(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Initialise the Winbond W83977F chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void __init wb977_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) request_region(0x370, 2, "W83977AF configuration");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Open up the SuperIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) wb977_open();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Initialise the global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) wb977_init_global();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Initialise the various devices in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * the multi-IO chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) wb977_init_printer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) wb977_init_keyboard();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) wb977_init_irda();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) wb977_init_gpio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Close up the EFER gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) wb977_close();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void nw_cpld_modify(unsigned int mask, unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) current_cpld = (current_cpld & ~mask) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) nw_gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) nw_gpio_modify_op(GPIO_IOLOAD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (msk = 8; msk; msk >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int bit = current_cpld & msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) nw_gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) nw_gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) nw_gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) nw_gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) nw_gpio_modify_op(GPIO_IOLOAD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) EXPORT_SYMBOL(nw_cpld_modify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void __init cpld_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) raw_spin_lock_irqsave(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static unsigned char rwa_unlock[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x00, 0x00, 0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #ifndef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define dprintk(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define dprintk(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define WRITE_RWA(r,v) do { outb((r), 0x279); udelay(10); outb((v), 0xa79); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline void rwa010_unlock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) WRITE_RWA(2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (i = 0; i < sizeof(rwa_unlock); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) outb(rwa_unlock[i], 0x279);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static inline void rwa010_read_ident(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned char si[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) WRITE_RWA(3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) WRITE_RWA(0, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) outb(1, 0x279);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dprintk("Identifier: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) si[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bit = inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dprintk("%02X ", bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bit = (bit == 0xaa) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) si[i] |= bit << j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dprintk("(%02X) ", si[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dprintk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static inline void rwa010_global_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) WRITE_RWA(6, 2); // Assign a card no = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dprintk("Card no = %d\n", inb(0x203));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* disable the modem section of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) WRITE_RWA(7, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) WRITE_RWA(0x30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* disable the cdrom section of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) WRITE_RWA(7, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) WRITE_RWA(0x30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* disable the MPU-401 section of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) WRITE_RWA(7, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) WRITE_RWA(0x30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static inline void rwa010_game_port_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) WRITE_RWA(7, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dprintk("Slider base: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) WRITE_RWA(0x61, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i = inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) WRITE_RWA(0x60, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dprintk("%02X%02X (201)\n", inb(0x203), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) WRITE_RWA(0x30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static inline void rwa010_waveartist_init(int base, int irq, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) WRITE_RWA(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dprintk("WaveArtist base: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) WRITE_RWA(0x61, base & 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) i = inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) WRITE_RWA(0x60, base >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dprintk("%02X%02X (%X),", inb(0x203), i, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) WRITE_RWA(0x70, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dprintk(" irq: %d (%d),", inb(0x203), irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) WRITE_RWA(0x74, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dprintk(" dma: %d (%d)\n", inb(0x203), dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) WRITE_RWA(0x30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static inline void rwa010_soundblaster_init(int sb_base, int al_base, int irq, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) WRITE_RWA(7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dprintk("SoundBlaster base: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) WRITE_RWA(0x61, sb_base & 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) i = inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) WRITE_RWA(0x60, sb_base >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dprintk("%02X%02X (%X),", inb(0x203), i, sb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dprintk(" irq: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) WRITE_RWA(0x70, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dprintk("%d (%d),", inb(0x203), irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dprintk(" 8-bit DMA: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) WRITE_RWA(0x74, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dprintk("%d (%d)\n", inb(0x203), dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dprintk("AdLib base: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) WRITE_RWA(0x63, al_base & 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) i = inb(0x203);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) WRITE_RWA(0x62, al_base >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dprintk("%02X%02X (%X)\n", inb(0x203), i, al_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) WRITE_RWA(0x30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void rwa010_soundblaster_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) outb(1, 0x226);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) outb(0, 0x226);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (inb(0x22e) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (i == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) printk("SoundBlaster: DSP reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dprintk("SoundBlaster DSP reset: %02X (AA)\n", inb(0x22a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if ((inb(0x22c) & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (i == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) printk("SoundBlaster: DSP not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) outb(0xe1, 0x22c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dprintk("SoundBlaster DSP id: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) i = inb(0x22a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) i |= inb(0x22a) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dprintk("%04X\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if ((inb(0x22c) & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (i == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) printk("SoundBlaster: could not turn speaker off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) outb(0xd3, 0x22c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* turn on OPL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) outb(5, 0x38a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) outb(1, 0x38b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void __init rwa010_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) rwa010_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rwa010_read_ident();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) rwa010_global_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rwa010_game_port_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rwa010_waveartist_init(0x250, 3, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rwa010_soundblaster_init(0x220, 0x388, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) rwa010_soundblaster_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * Initialise any other hardware after we've got the PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * initialised. We may need the PCI bus to talk to this other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int __init nw_hw_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (machine_is_netwinder()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) wb977_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cpld_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rwa010_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __initcall(nw_hw_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * Older NeTTroms either do not provide a parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * page, or they don't supply correct information in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * the parameter page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) fixup_netwinder(struct tag *tags, char **cmdline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #ifdef CONFIG_ISAPNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) extern int isapnp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * We must not use the kernels ISAPnP code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * on the NetWinder - it will reset the settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * for the WaveArtist chip and render it inoperable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) isapnp_disable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void netwinder_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (mode == REBOOT_SOFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Jump into the ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) soft_restart(0x41000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) local_fiq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* open up the SuperIO chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) outb(0x87, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) outb(0x87, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* aux function group 1 (logical device 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) outb(0x07, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) outb(0x07, 0x371);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* set GP16 for WD-TIMER output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) outb(0xe6, 0x370);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) outb(0x00, 0x371);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* set a RED LED and toggle WD_TIMER for rebooting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) outb(0xc4, 0x338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct netwinder_led {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct led_classdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * The triggers lines up below will only be used if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * LED triggers are compiled in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) const char *trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } netwinder_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { "netwinder:green", "heartbeat", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { "netwinder:red", "cpu0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * The LED control in Netwinder is reversed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * - setting bit means turn off LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * - clearing bit means turn on LED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void netwinder_led_set(struct led_classdev *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) enum led_brightness b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct netwinder_led *led = container_of(cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct netwinder_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) raw_spin_lock_irqsave(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) reg = nw_gpio_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (b != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) reg &= ~led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) reg |= led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) nw_gpio_modify_op(led->mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct netwinder_led *led = container_of(cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct netwinder_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) raw_spin_lock_irqsave(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) reg = nw_gpio_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return (reg & led->mask) ? LED_OFF : LED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int __init netwinder_leds_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!machine_is_netwinder())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct netwinder_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) led = kzalloc(sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) led->cdev.name = netwinder_leds[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) led->cdev.brightness_set = netwinder_led_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) led->cdev.brightness_get = netwinder_led_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) led->cdev.default_trigger = netwinder_leds[i].trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) led->mask = GPIO_GREEN_LED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) led->mask = GPIO_RED_LED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (led_classdev_register(NULL, &led->cdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) kfree(led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Since we may have triggers on any subsystem, defer registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * until after subsystem_init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fs_initcall(netwinder_leds_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MACHINE_START(NETWINDER, "Rebel-NetWinder")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Maintainer: Russell King/Rebel.com */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .video_start = 0x000a0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .video_end = 0x000bffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .reserve_lp0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .reserve_lp2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .fixup = fixup_netwinder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .map_io = footbridge_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .init_irq = footbridge_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .init_time = isa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .restart = netwinder_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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