Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  arch/arm/mach-footbridge/isa-rtc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1998 Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 1998 Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * CATS has a real-time clock, though the evaluation board doesn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Changelog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *  21-Mar-1998	RMK	Created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *  27-Aug-1998	PJB	CATS support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *  28-Dec-1998	APH	Made leds optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *  20-Jan-1999	RMK	Started merge of EBSA285, CATS and NetWinder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *  16-Mar-1999	RMK	More support for EBSA285-like machines with RTCs in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTC_PORT(x)		(0x70+(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_ALWAYS_BCD		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mc146818rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __init isa_rtc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	int reg_d, reg_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * Probe for the RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	reg_d = CMOS_READ(RTC_REG_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * make sure the divider is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	 * Set control reg B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	 *   (24 hour mode, update enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	reg_b = CMOS_READ(RTC_REG_B) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	reg_b |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	CMOS_WRITE(reg_b, RTC_REG_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	    CMOS_READ(RTC_REG_B) == reg_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		 * We have a RTC.  Check the battery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		if ((reg_d & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			printk(KERN_WARNING "RTC: *** warning: CMOS battery bad\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }