^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2001 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998-2000 Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MAX_SLOTS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PCI_STATUS_REC_TARGET_ABORT)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PCI_STATUS_REC_MASTER_ABORT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PCI_STATUS_REC_TARGET_ABORT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PCI_STATUS_PARITY) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern int setup_arm_irq(int, struct irqaction *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (PCI_SLOT(devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * For devfn 0, point at the 21285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) addr = ARMCSR_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) devfn -= 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long addr = dc21285_base_address(bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 v = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) asm volatile("ldrb %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) : "=r" (v) : "r" (addr), "r" (where) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) asm volatile("ldrh %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) : "=r" (v) : "r" (addr), "r" (where) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) asm volatile("ldr %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) : "=r" (v) : "r" (addr), "r" (where) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *value = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) v = *CSR_PCICMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (v & PCICMD_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long addr = dc21285_base_address(bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) asm volatile("strb %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : : "r" (value), "r" (addr), "r" (where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) asm volatile("strh %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) : : "r" (value), "r" (addr), "r" (where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) asm volatile("str %0, [%1, %2]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) : : "r" (value), "r" (addr), "r" (where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) v = *CSR_PCICMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (v & PCICMD_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pci_ops dc21285_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .read = dc21285_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .write = dc21285_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct timer_list serr_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct timer_list perr_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void dc21285_enable_error(struct timer_list *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) del_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (timer == &serr_timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enable_irq(IRQ_PCI_SERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else if (timer == &perr_timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enable_irq(IRQ_PCI_PERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Warn on PCI errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cmd = *CSR_PCICMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) status = cmd >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cmd = cmd & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (status & PCI_STATUS_REC_MASTER_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) instruction_pointer(get_irq_regs()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (status & PCI_STATUS_REC_TARGET_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) printk(KERN_DEBUG "PCI: target abort: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PCI_STATUS_SIG_TARGET_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PCI_STATUS_REC_TARGET_ABORT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *CSR_PCICMD = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct timer_list *timer = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) printk(KERN_DEBUG "PCI: system error received: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cntl = *CSR_SA110_CNTL & 0xffffdf07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * back off this interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) timer->expires = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) add_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) printk(KERN_DEBUG "PCI: discard timer expired\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *CSR_SA110_CNTL &= 0xffffde07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) printk(KERN_DEBUG "PCI: data parity error detected: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cmd = *CSR_PCICMD & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *CSR_PCICMD = cmd | 1 << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct timer_list *timer = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) printk(KERN_DEBUG "PCI: parity error detected: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cmd = *CSR_PCICMD & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *CSR_PCICMD = cmd | 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * back off this interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) timer->expires = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) add_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int __init dc21285_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (nr || !footbridge_cfn_mode())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk("out of memory for root bus resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) res[0].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) res[0].name = "Footbridge non-prefetch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) res[1].name = "Footbridge prefetch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) allocate_resource(&iomem_resource, &res[1], 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) allocate_resource(&iomem_resource, &res[0], 0x40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sys->mem_offset = DC21285_PCI_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define dc21285_request_irq(_a, _b, _c, _d, _e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void __init dc21285_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int mem_size, mem_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int cfn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pcibios_min_mem = 0x81000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mem_size = (unsigned int)high_memory - PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (mem_mask >= mem_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * These registers need to be set up whether we're the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * central function or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *CSR_SDRAMBASEOFFSET = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *CSR_ROMBASEMASK = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *CSR_CSRBASEMASK = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *CSR_CSRBASEOFFSET = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *CSR_PCIADDR_EXTN = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cfn_mode = __footbridge_cfn_mode();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "central function" : "addin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (footbridge_cfn_mode()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Clear any existing errors - we aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * interested in historical data...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SA110_CNTL_RXSERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) timer_setup(&serr_timer, dc21285_enable_error, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) timer_setup(&perr_timer, dc21285_enable_error, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * We don't care if these fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "PCI system error", &serr_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "PCI parity error", &perr_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "PCI abort", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "Discard timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "PCI data parity", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (cfn_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Map our SDRAM at a known address in PCI space, just in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * the firmware had other ideas. Using a nonzero base is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * necessary, since some VGA cards forcefully use PCI addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *CSR_PCICSRBASE = 0xf4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *CSR_PCICSRIOBASE = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *CSR_PCIROMBASE = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else if (footbridge_cfn_mode() != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * If we are not compiled to accept "add-in" mode, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * we are using a constant virt_to_bus translation which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * can not hope to cater for the way the host BIOS has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * set up the machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) panic("PCI: this kernel is compiled for central "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "function mode only");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __init dc21285_postinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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