^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-footbridge/dc21285-timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Phil Blundell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static u64 cksrc_dc21285_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return cs->mask - *CSR_TIMER2_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int cksrc_dc21285_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *CSR_TIMER2_LOAD = cs->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *CSR_TIMER2_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void cksrc_dc21285_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *CSR_TIMER2_CNTL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct clocksource cksrc_dc21285 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "dc21285_timer2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .read = cksrc_dc21285_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .enable = cksrc_dc21285_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .disable = cksrc_dc21285_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .mask = CLOCKSOURCE_MASK(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int ckevt_dc21285_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clock_event_device *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *CSR_TIMER1_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *CSR_TIMER1_LOAD = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ckevt_dc21285_shutdown(struct clock_event_device *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *CSR_TIMER1_CNTL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *CSR_TIMER1_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TIMER_CNTL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct clock_event_device ckevt_dc21285 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "dc21285_timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .irq = IRQ_TIMER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .set_next_event = ckevt_dc21285_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .set_state_shutdown = ckevt_dc21285_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .set_state_periodic = ckevt_dc21285_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .set_state_oneshot = ckevt_dc21285_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .tick_resume = ckevt_dc21285_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static irqreturn_t timer1_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clock_event_device *ce = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *CSR_TIMER1_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Stop the timer if in one-shot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (clockevent_state_oneshot(ce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *CSR_TIMER1_CNTL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Set up timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __init footbridge_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clock_event_device *ce = &ckevt_dc21285;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clocksource_register_hz(&cksrc_dc21285, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "dc21285_timer1", &ckevt_dc21285))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ce->cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static u64 notrace footbridge_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ~*CSR_TIMER3_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __init footbridge_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *CSR_TIMER3_LOAD = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *CSR_TIMER3_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sched_clock_register(footbridge_read_sched_clock, 24, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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