^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-footbridge/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998-2000 Russell King, Dave Gilbert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/hardware/dec21285.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int mem_fclk_21285 = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) EXPORT_SYMBOL(mem_fclk_21285);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int __init early_fclk(char *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) early_param("mem_fclk_21285", early_fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int __init parse_tag_memclk(const struct tag *tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mem_fclk_21285 = tag->u.memclk.fmemclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __tagtable(ATAG_MEMCLK, parse_tag_memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Footbridge IRQ translation table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Converts from our IRQ numbers into FootBridge masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const int fb_irq_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IRQ_MASK_UART_RX, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IRQ_MASK_UART_TX, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IRQ_MASK_TIMER1, /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IRQ_MASK_TIMER2, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IRQ_MASK_TIMER3, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IRQ_MASK_IN0, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IRQ_MASK_IN1, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) IRQ_MASK_IN2, /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) IRQ_MASK_IN3, /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) IRQ_MASK_DOORBELLHOST, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) IRQ_MASK_DMA1, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) IRQ_MASK_DMA2, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) IRQ_MASK_PCI, /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) IRQ_MASK_SDRAMPARITY, /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IRQ_MASK_I2OINPOST, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IRQ_MASK_PCI_ABORT, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IRQ_MASK_PCI_SERR, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IRQ_MASK_DISCARD_TIMER, /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IRQ_MASK_PCI_DPERR, /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IRQ_MASK_PCI_PERR, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void fb_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void fb_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct irq_chip fb_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_ack = fb_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .irq_mask = fb_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .irq_unmask = fb_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void __init __fb_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * setup DC21285 IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *CSR_IRQ_DISABLE = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *CSR_FIQ_DISABLE = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __init footbridge_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __fb_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!footbridge_cfn_mode())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (machine_is_ebsa285())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* The following is dependent on which slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * you plug the Southbridge card into. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * currently assume that you plug it into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * the right-hand most slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) isa_init_irq(IRQ_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (machine_is_cats())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) isa_init_irq(IRQ_IN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (machine_is_netwinder())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) isa_init_irq(IRQ_IN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Common mapping for all systems. Note that the outbound write flush is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * commented out since there is a "No Fix" problem with it. Not mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * it means that we have extra bullet protection on our feet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct map_desc fb_common_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .virtual = ARMCSR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .length = ARMCSR_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * The mapping when the footbridge is in host mode. We don't map any of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * this when we are in add-in mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct map_desc ebsa285_host_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .virtual = PCIMEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .pfn = __phys_to_pfn(DC21285_PCI_MEM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .length = PCIMEM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .virtual = PCICFG0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .length = PCICFG0_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .virtual = PCICFG1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .length = PCICFG1_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .virtual = PCIIACK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pfn = __phys_to_pfn(DC21285_PCI_IACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .length = PCIIACK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void __init footbridge_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Set up the common mapping first; we need this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * determine whether we're in host mode or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Now, work out what we've got to map in addition on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (footbridge_cfn_mode()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) vga_base = PCIMEM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void footbridge_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (mode == REBOOT_SOFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Jump into the ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) soft_restart(0x41000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Force the watchdog to do a CPU reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * After making sure that the watchdog is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * (so we can change the timer registers) we first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * enable the timer to autoreload itself. Next, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * timer interval is set really short and any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * current interrupt request is cleared (so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * see an edge transition). Finally, TIMER4 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * enabled as the watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *CSR_SA110_CNTL &= ~(1 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) TIMER_CNTL_AUTORELOAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TIMER_CNTL_DIV16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *CSR_TIMER4_LOAD = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *CSR_TIMER4_CLR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *CSR_SA110_CNTL |= (1 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifdef CONFIG_FOOTBRIDGE_ADDIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline unsigned long fb_bus_sdram_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return *CSR_PCISDRAMBASE & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * These two functions convert virtual addresses to PCI addresses and PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * addresses to virtual addresses. Note that it is only legal to use these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * on memory obtained via get_zeroed_page or kmalloc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long __virt_to_bus(unsigned long res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return res + (fb_bus_sdram_offset() - PAGE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) EXPORT_SYMBOL(__virt_to_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long __bus_to_virt(unsigned long res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) res = res - (fb_bus_sdram_offset() - PAGE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) WARN_ON(res < PAGE_OFFSET || res >= (unsigned long)high_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL(__bus_to_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long __pfn_to_bus(unsigned long pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) EXPORT_SYMBOL(__pfn_to_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long __bus_to_pfn(unsigned long bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return __phys_to_pfn(bus - (fb_bus_sdram_offset() - PHYS_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXPORT_SYMBOL(__bus_to_pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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