^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Exynos low-level resume code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "smc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_MASK 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CPU_CORTEX_A9 0x410fc090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * sleep magic, to allow the bootloader to check for an valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * image to resume to. Must be the first word before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * exynos_cpu_resume entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .word 0x2bedf00d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * exynos_cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * resume code entry for bootloader to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ENTRY(exynos_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mrc p15, 0, r0, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ldr r1, =CPU_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) and r0, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ldr r1, =CPU_CORTEX_A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bleq l2c310_early_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) b cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ENDPROC(exynos_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ENTRY(exynos_cpu_resume_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mrc p15, 0, r0, c0, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ldr r1, =CPU_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) and r0, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ldr r1, =CPU_CORTEX_A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bne skip_cp15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) adr r0, _cp15_save_power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ldr r1, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ldr r1, [r0, r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) adr r0, _cp15_save_diag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ldr r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ldr r2, [r0, r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mov r0, #SMC_CMD_C15RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) adr r0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ldr r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) add r0, r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Check that the address has been initialised. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ldr r1, [r0, #L2X0_R_PHY_BASE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) teq r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) beq skip_l2x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Check if controller has been enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ldr r2, [r1, #L2X0_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tst r2, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bne skip_l2x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ldr r1, [r0, #L2X0_R_TAG_LATENCY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldr r2, [r0, #L2X0_R_DATA_LATENCY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mov r0, #SMC_CMD_L2X0SETUP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Reload saved regs pointer because smc corrupts registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) adr r0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ldr r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) add r0, r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ldr r1, [r0, #L2X0_R_PWR_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ldr r2, [r0, #L2X0_R_AUX_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mov r0, #SMC_CMD_L2X0SETUP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mov r0, #SMC_CMD_L2X0INVALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mov r1, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mov r0, #SMC_CMD_L2X0CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) skip_l2x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif /* CONFIG_CACHE_L2X0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) skip_cp15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) b cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ENDPROC(exynos_cpu_resume_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) _cp15_save_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .long cp15_save_power - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) _cp15_save_diag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .long cp15_save_diag - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 1: .long l2x0_saved_regs - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif /* CONFIG_CACHE_L2X0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .globl cp15_save_diag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cp15_save_diag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .long 0 @ cp15 diagnostic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .globl cp15_save_power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cp15_save_power:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .long 0 @ cp15 power control
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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