Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Exynos - Power Management support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // Based on arch/arm/mach-s3c2410/pm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // Copyright (c) 2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/soc/samsung/exynos-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline void __iomem *exynos_boot_vector_addr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (exynos_rev() == EXYNOS4210_REV_1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		return pmu_base_addr + S5P_INFORM7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	else if (exynos_rev() == EXYNOS4210_REV_1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return sysram_base_addr + 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return pmu_base_addr + S5P_INFORM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static inline void __iomem *exynos_boot_vector_flag(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (exynos_rev() == EXYNOS4210_REV_1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		return pmu_base_addr + S5P_INFORM6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	else if (exynos_rev() == EXYNOS4210_REV_1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return sysram_base_addr + 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return pmu_base_addr + S5P_INFORM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define S5P_CHECK_AFTR  0xFCBA0D10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* For Cortex-A9 Diagnostic and Power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static unsigned int save_arm_register[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) void exynos_cpu_save_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* Save Power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	asm ("mrc p15, 0, %0, c15, c0, 0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	     : "=r" (tmp) : : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	save_arm_register[0] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Save Diagnostic register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	asm ("mrc p15, 0, %0, c15, c0, 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	     : "=r" (tmp) : : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	save_arm_register[1] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) void exynos_cpu_restore_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* Restore Power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	tmp = save_arm_register[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		      : : "r" (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		      : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Restore Diagnostic register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	tmp = save_arm_register[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		      : : "r" (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		      : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) void exynos_pm_central_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* Setting Central Sequence Register for power down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) int exynos_pm_central_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * If PMU failed while entering sleep mode, WFI will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * ignored by PMU and then exiting cpu_do_idle().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * in this situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		tmp |= S5P_CENTRAL_LOWPWR_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		/* clear the wakeup state register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		/* No need to perform below restore code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void exynos_set_wakeupmask(long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pmu_raw_writel(mask, S5P_WAKEUP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void exynos_cpu_set_boot_vector(long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	writel_relaxed(__pa_symbol(exynos_cpu_resume),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		       exynos_boot_vector_addr());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel_relaxed(flags, exynos_boot_vector_flag());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int exynos_aftr_finisher(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* Set value of power down register for aftr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	exynos_sys_powerdown_conf(SYS_AFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret == -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			exynos_cpu_save_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void exynos_enter_aftr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned int cpuid = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	cpu_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		exynos_set_boot_flag(cpuid, C2_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	exynos_pm_central_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (soc_is_exynos4412()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		/* Setting SEQ_OPTION register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			       S5P_CENTRAL_SEQ_OPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cpu_suspend(0, exynos_aftr_finisher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		exynos_scu_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (call_firmware_op(resume) == -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			exynos_cpu_restore_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	exynos_pm_central_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		exynos_clear_boot_flag(cpuid, C2_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	cpu_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int exynos_cpu0_enter_aftr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * If the other cpu is powered on, we have to power it off, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * the AFTR state won't work otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (cpu_online(1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 * We reach a sync point with the coupled idle state, we know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 * the other cpu will power down itself or will abort the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		 * sequence, let's wait for one of these to happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		while (exynos_cpu_power_state(1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			unsigned long boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			 * The other cpu may skip idle and boot back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			 * up again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			if (atomic_read(&cpu1_wakeup))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			 * The other cpu may bounce through idle and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			 * boot back up again, getting stuck in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			 * boot rom code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			ret = exynos_get_boot_addr(1, &boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			if (boot_addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	exynos_enter_aftr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (cpu_online(1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		 * Set the boot vector to something non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ret = exynos_set_boot_addr(1, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		 * Turn on cpu1 and wait for it to be on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		exynos_cpu_power_up(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (soc_is_exynos3250()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			while (!pmu_raw_readl(S5P_PMU_SPARE2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			       !atomic_read(&cpu1_wakeup))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			if (!atomic_read(&cpu1_wakeup))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				exynos_core_restart(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		while (!atomic_read(&cpu1_wakeup)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			 * Poke cpu1 out of the boot rom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			ret = exynos_set_boot_addr(1, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			call_firmware_op(cpu_boot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			dsb_sev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int exynos_wfi_finisher(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int exynos_cpu1_powerdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 * Idle sequence for cpu1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (cpu_pm_enter())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		goto cpu1_aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * Turn off cpu 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	exynos_cpu_power_down(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		pmu_raw_writel(0, S5P_PMU_SPARE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ret = cpu_suspend(0, exynos_wfi_finisher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	cpu_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cpu1_aborted:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * Notify cpu 0 that cpu 1 is awake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	atomic_set(&cpu1_wakeup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void exynos_pre_enter_aftr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	(void)exynos_set_boot_addr(1, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void exynos_post_enter_aftr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	atomic_set(&cpu1_wakeup, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.cpu0_enter_aftr		= exynos_cpu0_enter_aftr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.cpu1_powerdown		= exynos_cpu1_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.pre_enter_aftr		= exynos_pre_enter_aftr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.post_enter_aftr		= exynos_post_enter_aftr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */