Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) //		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Cloned from linux/arch/arm/mach-vexpress/platsmp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //  Copyright (C) 2002 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //  All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) extern void exynos4_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) volatile int exynos_pen_release = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static inline void cpu_leave_lowpower(u32 core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"mrc	p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	"	orr	%0, %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	"	mcr	p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	"	mrc	p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	"	orr	%0, %0, %2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	"	mcr	p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	  : "=&r" (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	  : "Ir" (CR_C), "Ir" (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 mpidr = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		/* Turn the CPU off on next WFI instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		exynos_cpu_power_down(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		if (exynos_pen_release == core_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			 * OK, proper wakeup, we're done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 * Getting here, means that we have come out of WFI without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 * having been woken up - this shouldn't happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 * Just note it happening - when we're woken, we can report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		 * its occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		(*spurious)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * exynos_core_power_down : power down the specified cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @cpu : the cpu to power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * Power down the specified cpu. The sequence must be finished by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * call to cpu_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) void exynos_cpu_power_down(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 core_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * Bypass power down for CPU0 during suspend. Check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * the SYS_PWR_REG value to decide if we are suspending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (!(val & S5P_CORE_LOCAL_PWR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * exynos_cpu_power_up : power up the specified cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * @cpu : the cpu to power up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * Power up the specified cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void exynos_cpu_power_up(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		core_conf |= S5P_CORE_AUTOWAKEUP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pmu_raw_writel(core_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			EXYNOS_ARM_CORE_CONFIGURATION(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * exynos_cpu_power_state : returns the power state of the cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * @cpu : the cpu to retrieve the power state from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int exynos_cpu_power_state(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			S5P_CORE_LOCAL_PWR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * exynos_cluster_power_down : power down the specified cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * @cluster : the cluster to power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void exynos_cluster_power_down(int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * exynos_cluster_power_up : power up the specified cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * @cluster : the cluster to power up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void exynos_cluster_power_up(int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			EXYNOS_COMMON_CONFIGURATION(cluster));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * exynos_cluster_power_state : returns the power state of the cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * @cluster : the cluster to retrieve the power state from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int exynos_cluster_power_state(int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		S5P_CORE_LOCAL_PWR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * exynos_scu_enable : enables SCU for Cortex-A9 based system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void exynos_scu_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	static void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!scu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			scu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			scu_base = ioremap(scu_a9_get_base(), SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void __iomem *cpu_boot_reg_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (soc_is_exynos4210() && exynos_rev() == EXYNOS4210_REV_1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return pmu_base_addr + S5P_INFORM5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return sysram_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline void __iomem *cpu_boot_reg(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	void __iomem *boot_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	boot_reg = cpu_boot_reg_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!boot_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return IOMEM_ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (soc_is_exynos4412())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		boot_reg += 4*cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	else if (soc_is_exynos5420() || soc_is_exynos5800())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		boot_reg += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return boot_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * Set wake up by local power mode and execute software reset for given core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * Currently this is needed only when booting secondary CPU on Exynos3250.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void exynos_core_restart(u32 core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned int timeout = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!of_machine_is_compatible("samsung,exynos3250"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		pr_err("cpu core %u restart failed\n", core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * XXX CARGO CULTED CODE - DO NOT COPY XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * Write exynos_pen_release in a way that is guaranteed to be visible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * all observers, irrespective of whether they're taking part in coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * or not.  This is necessary for the hotplug code to work reliably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void exynos_write_pen_release(int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	exynos_pen_release = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	sync_cache_w(&exynos_pen_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static DEFINE_SPINLOCK(boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void exynos_secondary_init(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * let the primary processor know we're out of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * pen, then head off into the C entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	exynos_write_pen_release(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * Synchronise with the boot thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spin_lock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	spin_unlock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * Try to set boot address using firmware first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 * and fall back to boot register if it fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret && ret != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret == -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		void __iomem *boot_reg = cpu_boot_reg(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (IS_ERR(boot_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			ret = PTR_ERR(boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		writel_relaxed(boot_addr, boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * Try to get boot address using firmware first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * and fall back to boot register if it fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	ret = call_firmware_op(get_cpu_boot_addr, core_id, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (ret && ret != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret == -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		void __iomem *boot_reg = cpu_boot_reg(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		if (IS_ERR(boot_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			ret = PTR_ERR(boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		*boot_addr = readl_relaxed(boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	u32 mpidr = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int ret = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 * Set synchronisation state between this boot processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 * and the secondary one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	spin_lock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	 * The secondary processor is waiting to be released from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	 * the holding pen - release it, then wait for it to flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	 * that it has been released by resetting exynos_pen_release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	 * Note that "exynos_pen_release" is the hardware CPU core ID, whereas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	 * "cpu" is Linux's internal ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	exynos_write_pen_release(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (!exynos_cpu_power_state(core_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		exynos_cpu_power_up(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		/* wait max 10 ms until cpu1 is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		while (exynos_cpu_power_state(core_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		       != S5P_CORE_LOCAL_PWR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			printk(KERN_ERR "cpu1 power enable failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			spin_unlock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	exynos_core_restart(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	 * Send the secondary CPU a soft interrupt, thereby causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * the boot monitor to read the system wide flags register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * and branch to the address found there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	timeout = jiffies + (1 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		unsigned long boot_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		boot_addr = __pa_symbol(exynos4_secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ret = exynos_set_boot_addr(core_id, boot_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		call_firmware_op(cpu_boot, core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			dsb_sev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		if (exynos_pen_release == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (exynos_pen_release != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 * now the secondary core is starting up let it run its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 * calibrations, then wait for it to finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	spin_unlock(&boot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	return exynos_pen_release != -1 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	exynos_sysram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	exynos_set_delayed_reset_assertion(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		exynos_scu_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)  * platform-specific code to shutdown a CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)  * Called with IRQs disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void exynos_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int spurious = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	u32 mpidr = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	platform_do_lowpower(cpu, &spurious);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	 * bring this CPU back into the world of cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	 * coherency, and then restore interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	cpu_leave_lowpower(core_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (spurious)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) const struct smp_operations exynos_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.smp_prepare_cpus	= exynos_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	.smp_secondary_init	= exynos_secondary_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.smp_boot_secondary	= exynos_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.cpu_die		= exynos_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };