Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) //		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Based on arch/arm/mach-vexpress/dcscb.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/arm-cci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/mcpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define EXYNOS5420_CPUS_PER_CLUSTER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define EXYNOS5420_NR_CLUSTERS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE	BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define EXYNOS5420_USE_L2_COMMON_UP_STATE	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void __iomem *ns_sram_base_addr __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static bool secure_firmware __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * The common v7_exit_coherency_flush API could not be used because of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * Erratum 799270 workaround. This macro is the same as the common one (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define exynos_v7_exit_coherency_flush(level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	asm volatile( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"stmfd	sp!, {fp, ip}\n\t"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	"isb\n\t"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* Dummy Load of a device register to avoid Erratum 799270 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	"ldr	r4, [%0]\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	"and	r4, r4, #0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	"orr	r0, r0, r4\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	"isb\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	"dsb\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	"ldmfd	sp!, {fp, ip}" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	: "Ir" (pmu_base_addr + S5P_INFORM0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	  "r9", "r10", "lr", "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	bool state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		cluster >= EXYNOS5420_NR_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	state = exynos_cpu_power_state(cpunr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	exynos_cpu_power_up(cpunr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!state && secure_firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		 * This assumes the cluster number of the big cores(Cortex A15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		 * is 0 and the Little cores(Cortex A7) is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		 * When the system was booted from the Little core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		 * they should be reset during power up cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		if (cluster &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		    cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			unsigned int timeout = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			 * Before we reset the Little cores, we should wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			 * the SPARE2 register is set to 1 because the init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			 * codes of the iROM will set the register after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			 * initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				pr_err("cpu %u cluster %u powerup failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				       cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				exynos_cpu_power_down(cpunr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					EXYNOS_SWRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int exynos_cluster_powerup(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (cluster >= EXYNOS5420_NR_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	exynos_cluster_power_up(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			cluster >= EXYNOS5420_NR_CLUSTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	exynos_cpu_power_down(cpunr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void exynos_cluster_powerdown_prepare(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	exynos_cluster_power_down(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void exynos_cpu_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* Disable and flush the local CPU cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	exynos_v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void exynos_cluster_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		 * On the Cortex-A15 we need to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		 * L2 prefetching before flushing the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		"mcr	p15, 1, %0, c15, c0, 3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		"isb\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		"dsb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		: : "r" (0x400));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Flush all cache levels for this cluster. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	exynos_v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * Disable cluster-level coherency by masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * incoming snoops and DVM messages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	cci_disable_port_by_cpu(read_cpuid_mpidr());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int tries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			cluster >= EXYNOS5420_NR_CLUSTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Wait for the core state to be OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	while (tries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if ((exynos_cpu_power_state(cpunr) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			return 0; /* success: the CPU is halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		/* Otherwise, wait and retry: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return -ETIMEDOUT; /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* especially when resuming: make sure power control is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	exynos_cpu_powerup(cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct mcpm_platform_ops exynos_power_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.cpu_powerup		= exynos_cpu_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.cluster_powerup	= exynos_cluster_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.cpu_powerdown_prepare	= exynos_cpu_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.cpu_cache_disable	= exynos_cpu_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.cluster_cache_disable	= exynos_cluster_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.wait_for_powerdown	= exynos_wait_for_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.cpu_is_up		= exynos_cpu_is_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * Enable cluster-level coherency, in preparation for turning on the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	asm volatile ("\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	"cmp	r0, #1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	"bxne	lr\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	"b	cci_enable_port_for_self");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct of_device_id exynos_dt_mcpm_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ .compatible = "samsung,exynos5420" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ .compatible = "samsung,exynos5800" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void exynos_mcpm_setup_entry_point(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 * as part of secondary_cpu_start().  Let's redirect it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 * mcpm_entry_point(). This is done during both secondary boot-up as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * well as system resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	__raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	__raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct syscore_ops exynos_mcpm_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.resume	= exynos_mcpm_setup_entry_point,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int __init exynos_mcpm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	unsigned int value, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (!cci_probed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	node = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			"samsung,exynos4210-sysram-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ns_sram_base_addr = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!ns_sram_base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pr_err("failed to map non-secure iRAM base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	secure_firmware = exynos_secure_firmware_available();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * To increase the stability of KFC reset we need to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * the PMU SPARE3 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = mcpm_platform_register(&exynos_power_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ret = mcpm_sync_init(exynos_pm_power_up_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		iounmap(ns_sram_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mcpm_smp_set_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	pr_info("Exynos MCPM support installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	 * On Exynos5420/5800 for the A15 and A7 clusters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * in a cluster are turned off before turning off the cluster L2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 * off before waking it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * turned on before the first man is powered up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			 EXYNOS5420_USE_ARM_CORE_DOWN_STATE    |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			 EXYNOS5420_USE_L2_COMMON_UP_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	exynos_mcpm_setup_entry_point();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	register_syscore_ops(&exynos_mcpm_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) early_initcall(exynos_mcpm_init);