Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (C) 2012 Samsung Electronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Kyungmin Park <kyungmin.park@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Tomasz Figa <t.figa@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "smc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define EXYNOS_BOOT_ADDR	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define EXYNOS_BOOT_FLAG	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static void exynos_save_cp15(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* Save Power control and Diagnostic registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	asm ("mrc p15, 0, %0, c15, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	     "mrc p15, 0, %1, c15, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	     : "=r" (cp15_save_power), "=r" (cp15_save_diag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	     : : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int exynos_do_idle(unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	case FW_DO_IDLE_AFTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			exynos_save_cp15();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			       sysram_ns_base_addr + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		if (soc_is_exynos3250()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				   SMC_POWERSTATE_IDLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 				   SMC_POWERSTATE_IDLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	case FW_DO_IDLE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int exynos_cpu_boot(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * because Exynos3250 removes WFE in secure mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (soc_is_exynos3250())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *boot_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (!sysram_ns_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	boot_reg = sysram_ns_base_addr + 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * Almost all Exynos-series of SoCs that run in secure mode don't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * additional offset for every CPU, with Exynos4412 being the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (soc_is_exynos4412())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		boot_reg += 4 * cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	writel_relaxed(boot_addr, boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	void __iomem *boot_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!sysram_ns_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	boot_reg = sysram_ns_base_addr + 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (soc_is_exynos4412())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		boot_reg += 4 * cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	*boot_addr = readl_relaxed(boot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int exynos_cpu_suspend(unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	outer_flush_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	pr_info("Failed to suspend the system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int exynos_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		exynos_save_cp15();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	writel(__pa_symbol(exynos_cpu_resume_ns),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return cpu_suspend(0, exynos_cpu_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int exynos_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct firmware_ops exynos_firmware_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.do_idle		= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.set_cpu_boot_addr	= exynos_set_cpu_boot_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.get_cpu_boot_addr	= exynos_get_cpu_boot_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.cpu_boot		= exynos_cpu_boot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.suspend		= IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.resume			= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void exynos_l2_write_sec(unsigned long val, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	static int l2cache_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	case L2X0_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (val & L2X0_CTRL_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			 * Before the cache can be enabled, due to firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			 * design, SMC_CMD_L2X0INVALL must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			if (!l2cache_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				l2cache_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			l2cache_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	case L2X0_DEBUG_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void exynos_l2_configure(const struct l2x0_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		   regs->prefetch_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bool __init exynos_secure_firmware_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct device_node *nd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	const __be32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	nd = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 					"samsung,secure-firmware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!nd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	addr = of_get_address(nd, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	of_node_put(nd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		pr_err("%s: No address specified.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __init exynos_firmware_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!exynos_secure_firmware_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	pr_info("Running under secure firmware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	register_firmware_ops(&exynos_firmware_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * running under secure firmware, require certain registers of L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * cache controller to be written in secure mode. Here .write_sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * callback is provided to perform necessary SMC calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	    read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		outer_cache.write_sec = exynos_l2_write_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		outer_cache.configure = exynos_l2_configure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define REG_CPU_STATE_ADDR	(sysram_ns_base_addr + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BOOT_MODE_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (mode & BOOT_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		tmp &= ~BOOT_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	tmp |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	tmp &= ~mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }