^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Timer handling for EP93xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * is free-running, and can't generate interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The 508 kHz timers are ideal for use for the timer interrupt, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * timer (timer 3) to get as long sleep intervals as possible when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * CONFIG_NO_HZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The higher clock rate of timer 4 makes it a better choice than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * other timers for use as clock source and for sched_clock(), providing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * a stable 40 bit time base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EP93XX_TIMER123_RATE 508469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EP93XX_TIMER4_RATE 983040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static u64 notrace ep93xx_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = readl(EP93XX_TIMER4_VALUE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u64 ep93xx_clocksource_read(struct clocksource *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = readl(EP93XX_TIMER4_VALUE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return (u64) ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int ep93xx_clkevt_set_next_event(unsigned long next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Default mode: periodic, off, 508 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) EP93XX_TIMER123_CONTROL_CLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Clear timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(tmode, EP93XX_TIMER3_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Set next event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(next, EP93XX_TIMER3_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EP93XX_TIMER3_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(0, EP93XX_TIMER3_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct clock_event_device ep93xx_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .features = CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .set_state_shutdown = ep93xx_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .set_state_oneshot = ep93xx_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .tick_resume = ep93xx_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .set_next_event = ep93xx_clkevt_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Writing any value clears the timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(1, EP93XX_TIMER3_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __init ep93xx_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int irq = IRQ_EP93XX_TIMER3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Enable and register clocksource and sched_clock on timer 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EP93XX_TIMER4_VALUE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clocksource_mmio_init(NULL, "timer4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) EP93XX_TIMER4_RATE, 200, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ep93xx_clocksource_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) sched_clock_register(ep93xx_read_sched_clock, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EP93XX_TIMER4_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Set up clockevent on timer 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &ep93xx_clockevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clockevents_config_and_register(&ep93xx_clockevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) EP93XX_TIMER123_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0xffffffffU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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