Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-ep93xx/soc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _EP93XX_SOC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _EP93XX_SOC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <mach/ep93xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * EP93xx Physical Memory Map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * The ASDO pin is sampled at system reset to select a synchronous or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * the synchronous boot mode is selected.  When ASDO is "0" (i.e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * pulled-down) the asynchronous boot mode is selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * In synchronous boot mode nSDCE3 is decoded starting at physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * decoded at 0xf0000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * There is known errata for the EP93xx dealing with External Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Guidelines" for more information.  This document can be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EP93XX_CS1_PHYS_BASE		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EP93XX_CS2_PHYS_BASE		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EP93XX_CS3_PHYS_BASE		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EP93XX_PCMCIA_PHYS_BASE		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EP93XX_CS6_PHYS_BASE		0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define EP93XX_CS7_PHYS_BASE		0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define EP93XX_SDCE0_PHYS_BASE		0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define EP93XX_SDCE1_PHYS_BASE		0xd0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define EP93XX_SDCE2_PHYS_BASE		0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* AHB peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define EP93XX_DMA_BASE			EP93XX_AHB_IOMEM(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define EP93XX_ETHERNET_PHYS_BASE	EP93XX_AHB_PHYS(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EP93XX_ETHERNET_BASE		EP93XX_AHB_IOMEM(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EP93XX_USB_PHYS_BASE		EP93XX_AHB_PHYS(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EP93XX_USB_BASE			EP93XX_AHB_IOMEM(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EP93XX_RASTER_PHYS_BASE		EP93XX_AHB_PHYS(0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define EP93XX_RASTER_BASE		EP93XX_AHB_IOMEM(0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EP93XX_GRAPHICS_ACCEL_BASE	EP93XX_AHB_IOMEM(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define EP93XX_SDRAM_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00060000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define EP93XX_PCMCIA_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define EP93XX_IDE_PHYS_BASE		EP93XX_AHB_PHYS(0x000a0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define EP93XX_VIC2_BASE		EP93XX_AHB_IOMEM(0x000c0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* APB peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define EP93XX_AAC_PHYS_BASE		EP93XX_APB_PHYS(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define EP93XX_SPI_PHYS_BASE		EP93XX_APB_PHYS(0x000a0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define EP93XX_SPI_BASE			EP93XX_APB_IOMEM(0x000a0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define EP93XX_IRDA_BASE		EP93XX_APB_IOMEM(0x000b0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define EP93XX_KEY_MATRIX_PHYS_BASE	EP93XX_APB_PHYS(0x000f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define EP93XX_KEY_MATRIX_BASE		EP93XX_APB_IOMEM(0x000f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define EP93XX_ADC_PHYS_BASE		EP93XX_APB_PHYS(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define EP93XX_ADC_BASE			EP93XX_APB_IOMEM(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define EP93XX_TOUCHSCREEN_BASE		EP93XX_APB_IOMEM(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define EP93XX_PWM_PHYS_BASE		EP93XX_APB_PHYS(0x00110000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define EP93XX_PWM_BASE			EP93XX_APB_IOMEM(0x00110000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EP93XX_RTC_PHYS_BASE		EP93XX_APB_PHYS(0x00120000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EP93XX_RTC_BASE			EP93XX_APB_IOMEM(0x00120000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* System controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EP93XX_I2SCLKDIV_LRDIV128	(2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EP93XX_I2SCLKDIV_LRDIV_MASK	(3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* EP93xx System Controller software locked register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline void ep93xx_devcfg_set_bits(unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ep93xx_devcfg_set_clear(bits, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ep93xx_devcfg_set_clear(0x00, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif /* _EP93XX_SOC_H */