^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-ep93xx/snappercl15.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Bluewater Systems Snapper CL15 system module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Bluewater Systems Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Ryan Mallon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * NAND code adapted from driver by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Andre Renaud <andre@bluewatersys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * James R. McKaskill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/video-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "gpio-ep93xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SNAPPERCL15_NAND_ALE (1 << 9) /* Address latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SNAPPERCL15_NAND_CLE (1 << 10) /* Command latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SNAPPERCL15_NAND_CEN (1 << 11) /* Chip enable (active low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SNAPPERCL15_NAND_RDY (1 << 14) /* Device ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NAND_CTRL_ADDR(chip) (chip->legacy.IO_ADDR_W + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void snappercl15_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static u16 nand_state = SNAPPERCL15_NAND_WPN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ctrl & NAND_CTRL_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ctrl & NAND_NCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) set &= ~SNAPPERCL15_NAND_CEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ctrl & NAND_CLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) set |= SNAPPERCL15_NAND_CLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ctrl & NAND_ALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) set |= SNAPPERCL15_NAND_ALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) nand_state &= ~(SNAPPERCL15_NAND_CEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SNAPPERCL15_NAND_CLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SNAPPERCL15_NAND_ALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) nand_state |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (cmd != NAND_CMD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writew((cmd & 0xff) | nand_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) chip->legacy.IO_ADDR_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int snappercl15_nand_dev_ready(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct mtd_partition snappercl15_nand_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "Kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "Filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct platform_nand_data snappercl15_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .partitions = snappercl15_nand_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .chip_delay = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .dev_ready = snappercl15_nand_dev_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .cmd_ctrl = snappercl15_nand_cmd_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct resource snappercl15_nand_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .start = SNAPPERCL15_NAND_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct platform_device snappercl15_nand_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .dev.platform_data = &snappercl15_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .resource = snappercl15_nand_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .num_resources = ARRAY_SIZE(snappercl15_nand_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ep93xx_eth_data __initdata snappercl15_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .phy_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Audio codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) I2C_BOARD_INFO("tlv320aic23", 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct platform_device snappercl15_audio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "snappercl15-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void __init snappercl15_register_audio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ep93xx_register_i2s();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) platform_device_register(&snappercl15_audio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void __init snappercl15_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ep93xx_init_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ep93xx_register_eth(&snappercl15_eth_data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ep93xx_register_i2c(snappercl15_i2c_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ARRAY_SIZE(snappercl15_i2c_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ep93xx_register_fb(&snappercl15_fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) snappercl15_register_audio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) platform_device_register(&snappercl15_nand_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Maintainer: Ryan Mallon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .map_io = ep93xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .init_irq = ep93xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .init_time = ep93xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .init_machine = snappercl15_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .init_late = ep93xx_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .restart = ep93xx_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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