Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-ep93xx/include/mach/hardware.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASM_ARCH_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ASM_ARCH_HARDWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * The EP93xx has two external crystal oscillators.  To generate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * required high-frequency clocks, the processor uses two phase-locked-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * loops (PLLs) to multiply the incoming external clock signal to much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * higher frequencies that are then divided down by programmable dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * to produce the needed clocks.  The PLLs operate independently of one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * another.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EP93XX_EXT_CLK_RATE	14745600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EP93XX_EXT_RTC_RATE	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EP93XX_KEYTCHCLK_DIV4	(EP93XX_EXT_CLK_RATE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EP93XX_KEYTCHCLK_DIV16	(EP93XX_EXT_CLK_RATE / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif