^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-ep93xx/dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Platform support code for the EP93xx dmaengine driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2011 Mika Westerberg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This work is based on the original dma-m2p implementation with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * following copyrights:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2006 Applied Data Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/dma-ep93xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "hardware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMA_CHANNEL(_name, _base, _irq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .name = (_name), .base = (_base), .irq = (_irq) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * DMA M2P channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * On the EP93xx chip the following peripherals my be allocated to the 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * I2S contains 3 Tx and 3 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * AAC contains 3 Tx and 3 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * UART1 contains 1 Tx and 1 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * UART2 contains 1 Tx and 1 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * UART3 contains 1 Tx and 1 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * IrDA contains 1 Tx and 1 Rx DMA Channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Registers are mapped statically in ep93xx_map_io().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .channels = ep93xx_dma_m2p_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct platform_device ep93xx_dma_m2p_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "ep93xx-dma-m2p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .platform_data = &ep93xx_dma_m2p_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .dma_mask = &ep93xx_dma_m2p_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * DMA M2M channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * There are 2 M2M channels which support memcpy/memset and in addition simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * hardware requests from/to SSP and IDE. We do not implement an external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * hardware requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Registers are mapped statically in ep93xx_map_io().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .channels = ep93xx_dma_m2m_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct platform_device ep93xx_dma_m2m_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "ep93xx-dma-m2m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .platform_data = &ep93xx_dma_m2m_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .dma_mask = &ep93xx_dma_m2m_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int __init ep93xx_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) platform_device_register(&ep93xx_dma_m2p_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) platform_device_register(&ep93xx_dma_m2m_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) arch_initcall(ep93xx_dma_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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