Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ASM_ARCH_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ASM_ARCH_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLOCK_GATING_CONTROL	(DOVE_PMU_VIRT_BASE + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define  CLOCK_GATING_BIT_USB0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define  CLOCK_GATING_BIT_USB1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define  CLOCK_GATING_BIT_GBE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define  CLOCK_GATING_BIT_SATA		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define  CLOCK_GATING_BIT_PCIE0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define  CLOCK_GATING_BIT_PCIE1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define  CLOCK_GATING_BIT_SDIO0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define  CLOCK_GATING_BIT_SDIO1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define  CLOCK_GATING_BIT_NAND		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define  CLOCK_GATING_BIT_CAMERA	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define  CLOCK_GATING_BIT_I2S0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define  CLOCK_GATING_BIT_I2S1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define  CLOCK_GATING_BIT_CRYPTO	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define  CLOCK_GATING_BIT_AC97		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define  CLOCK_GATING_BIT_PDMA		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define  CLOCK_GATING_BIT_XOR0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define  CLOCK_GATING_BIT_XOR1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define  CLOCK_GATING_BIT_GIGA_PHY	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define  CLOCK_GATING_USB0_MASK		(1 << CLOCK_GATING_BIT_USB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define  CLOCK_GATING_USB1_MASK		(1 << CLOCK_GATING_BIT_USB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define  CLOCK_GATING_GBE_MASK		(1 << CLOCK_GATING_BIT_GBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define  CLOCK_GATING_SATA_MASK		(1 << CLOCK_GATING_BIT_SATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define  CLOCK_GATING_PCIE0_MASK	(1 << CLOCK_GATING_BIT_PCIE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define  CLOCK_GATING_PCIE1_MASK	(1 << CLOCK_GATING_BIT_PCIE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define  CLOCK_GATING_SDIO0_MASK	(1 << CLOCK_GATING_BIT_SDIO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define  CLOCK_GATING_SDIO1_MASK	(1 << CLOCK_GATING_BIT_SDIO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define  CLOCK_GATING_NAND_MASK		(1 << CLOCK_GATING_BIT_NAND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define  CLOCK_GATING_CAMERA_MASK	(1 << CLOCK_GATING_BIT_CAMERA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define  CLOCK_GATING_I2S0_MASK		(1 << CLOCK_GATING_BIT_I2S0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define  CLOCK_GATING_I2S1_MASK		(1 << CLOCK_GATING_BIT_I2S1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define  CLOCK_GATING_CRYPTO_MASK	(1 << CLOCK_GATING_BIT_CRYPTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define  CLOCK_GATING_AC97_MASK		(1 << CLOCK_GATING_BIT_AC97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define  CLOCK_GATING_PDMA_MASK		(1 << CLOCK_GATING_BIT_PDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define  CLOCK_GATING_XOR0_MASK		(1 << CLOCK_GATING_BIT_XOR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define  CLOCK_GATING_XOR1_MASK		(1 << CLOCK_GATING_BIT_XOR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define  CLOCK_GATING_GIGA_PHY_MASK	(1 << CLOCK_GATING_BIT_GIGA_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PMU_INTERRUPT_CAUSE	(DOVE_PMU_VIRT_BASE + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define  PMU_SW_RST_VIDEO_MASK		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define  PMU_SW_RST_GPU_MASK		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define  PMU_PWR_GPU_PWR_DWN_MASK	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define  PMU_PWR_VPU_PWR_DWN_MASK	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define  PMU_ISO_VIDEO_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define  PMU_ISO_GPU_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif