^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ARCH_DOVE_MPP_CODED_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ARCH_DOVE_MPP_CODED_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define MPP(_num, _sel, _in, _out) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* MPP number */ ((_num) & 0xff) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* MPP select value */ (((_sel) & 0xf) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* may be input signal */ ((!!(_in)) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* may be output signal */ ((!!(_out)) << 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MPP_MAX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* for MPP groups _num is a group index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum dove_mpp_grp_idx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MPP_24_39 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MPP_40_45 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MPP_46_51 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MPP_58_61 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MPP_62_63 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MPP_GRP_MAX = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* The MPP[64:71] control differs from other groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MPP_GRP_NFC_64_71_GPO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MPP_GRP_NFC_64_71_NFC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * The MPP[52:57] functionality is encoded by 4 bits in different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * registers. The _num field in this case encodes those bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * correspodence with Table 135 of 88AP510 Functional specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MPP_GRP_AU1_52_57_AU1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MPP_GRP_AU1_52_57_GPIO 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MPP_GRP_AU1_52_57_TW_GPIO 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MPP_GRP_AU1_52_57_AU1_SSP 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MPP_GRP_AU1_52_57_SSP_TW 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void dove_mpp_conf(unsigned int *mpp_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int *mpp_grp_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int grp_au1_52_57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int grp_nfc_64_71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif /* __ARCH_DOVE_MPP_CODED_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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