^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-dove/mpp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * MPP functions for Marvell Dove SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <plat/mpp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <plat/orion-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "dove.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct dove_mpp_grp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Map a group to a range of GPIO pins in that group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct dove_mpp_grp dove_mpp_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [MPP_24_39] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .start = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .end = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [MPP_40_45] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .start = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .end = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [MPP_46_51] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .start = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .end = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [MPP_58_61] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .start = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .end = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [MPP_62_63] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .start = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .end = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Enable gpio for a range of pins. mode should be a combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GPIO_OUTPUT_OK | GPIO_INPUT_OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) for (i = start; i <= end; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) orion_gpio_set_valid(i, gpio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Dump all the extra MPP registers. The platform code will dump the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) registers for pins 0-23. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __init dove_mpp_dump_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_debug("PMU_CTRL4_CTRL: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) readl(DOVE_MPP_CTRL4_VIRT_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) readl(DOVE_PMU_MPP_GENERAL_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void __init dove_mpp_cfg_nfc(int sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mpp_gen_cfg &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mpp_gen_cfg |= sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void __init dove_mpp_cfg_au1(int sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!sel || sel == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dove_mpp_gpio_mode(52, 57, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (sel & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dove_mpp_gpio_mode(56, 57, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (sel & 0x2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (sel & 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ssp_ctrl1 |= DOVE_SSP_ON_AU1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dove_mpp_gpio_mode(52, 55, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (sel & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Configure the group registers, enabling GPIO if sel indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pin is to be used for GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for ( ; *mpp_grp_list; mpp_grp_list++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int num = MPP_NUM(*mpp_grp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int sel = MPP_SEL(*mpp_grp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (num > MPP_GRP_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pr_err("dove: invalid MPP GRP number (%u)\n", num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mpp_ctrl4 &= ~(0x1 << num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mpp_ctrl4 |= sel << num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dove_mpp_gpio_mode(dove_mpp_grp[num].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dove_mpp_grp[num].end, gpio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Configure the various MPP pins on Dove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init dove_mpp_conf(unsigned int *mpp_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int *mpp_grp_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int grp_au1_52_57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int grp_nfc_64_71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dove_mpp_dump_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Use platform code for pins 0-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dove_mpp_conf_grp(mpp_grp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dove_mpp_cfg_au1(grp_au1_52_57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dove_mpp_cfg_nfc(grp_nfc_64_71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dove_mpp_dump_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags