^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * IRQ definitions for Marvell Dove 88AP510 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Dove Low Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IRQ_DOVE_BRIDGE (1 + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IRQ_DOVE_H2C (1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQ_DOVE_C2H (1 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IRQ_DOVE_NAND (1 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IRQ_DOVE_PDMA (1 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQ_DOVE_SPI1 (1 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IRQ_DOVE_SPI0 (1 + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_DOVE_UART_0 (1 + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQ_DOVE_UART_1 (1 + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_DOVE_UART_2 (1 + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_DOVE_UART_3 (1 + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_DOVE_I2C (1 + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_DOVE_GPIO_0_7 (1 + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQ_DOVE_GPIO_8_15 (1 + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQ_DOVE_GPIO_16_23 (1 + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQ_DOVE_PCIE0_ERR (1 + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IRQ_DOVE_PCIE0 (1 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_DOVE_PCIE1_ERR (1 + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_DOVE_PCIE1 (1 + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQ_DOVE_I2S0 (1 + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IRQ_DOVE_I2S0_ERR (1 + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_DOVE_I2S1 (1 + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_DOVE_I2S1_ERR (1 + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_DOVE_USB_ERR (1 + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_DOVE_USB0 (1 + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQ_DOVE_USB1 (1 + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQ_DOVE_GE00_RX (1 + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_DOVE_GE00_TX (1 + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_DOVE_GE00_MISC (1 + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_DOVE_GE00_SUM (1 + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IRQ_DOVE_GE00_ERR (1 + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IRQ_DOVE_CRYPTO (1 + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Dove High Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IRQ_DOVE_AC97 (1 + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IRQ_DOVE_PMU (1 + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRQ_DOVE_CAM (1 + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_DOVE_SDIO0 (1 + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_DOVE_SDIO1 (1 + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_DOVE_XOR_00 (1 + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IRQ_DOVE_XOR_01 (1 + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IRQ_DOVE_XOR0_ERR (1 + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IRQ_DOVE_XOR_10 (1 + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IRQ_DOVE_XOR_11 (1 + 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IRQ_DOVE_XOR1_ERR (1 + 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IRQ_DOVE_LCD_DCON (1 + 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IRQ_DOVE_LCD1 (1 + 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IRQ_DOVE_LCD0 (1 + 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IRQ_DOVE_GPU (1 + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IRQ_DOVE_PERFORM_MNTR (1 + 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IRQ_DOVE_VPRO_DMA1 (1 + 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IRQ_DOVE_SSP_TIMER (1 + 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IRQ_DOVE_SSP (1 + 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IRQ_DOVE_MC_L2_ERR (1 + 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IRQ_DOVE_CRYPTO_ERR (1 + 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IRQ_DOVE_GPIO_24_31 (1 + 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IRQ_DOVE_HIGH_GPIO (1 + 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IRQ_DOVE_SATA (1 + 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * DOVE General Purpose Pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IRQ_DOVE_GPIO_START 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NR_GPIO_IRQS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * PMU interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NR_PMU_IRQS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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