^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-dove/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Core functions for Marvell Dove 88AP510 System On Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/dma-mv_xor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/usb-ehci-orion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/soc/dove/pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hardware/cache-tauros2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <plat/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <plat/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <plat/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "bridge-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* These can go away once Dove uses the mvebu-mbus DT binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DOVE_MBUS_PCIE0_IO_TARGET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DOVE_MBUS_PCIE1_IO_TARGET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DOVE_MBUS_CESA_TARGET 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DOVE_MBUS_CESA_ATTR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DOVE_MBUS_BOOTROM_TARGET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DOVE_MBUS_BOOTROM_ATTR 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * I/O Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .length = DOVE_SB_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .length = DOVE_NB_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __init dove_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * CLK tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int dove_tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static DEFINE_SPINLOCK(gating_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct clk *tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk __init *dove_register_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *parent, u8 bit_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return clk_register_gate(NULL, name, parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (void __iomem *)CLOCK_GATING_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bit_idx, 0, &gating_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init dove_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *xor0, *xor1, *ge, *gephy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) orion_clkdev_add(NULL, "orion_spi.0", tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) orion_clkdev_add(NULL, "orion_spi.1", tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) orion_clkdev_add(NULL, "orion_wdt", tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) orion_clkdev_add(NULL, "orion-ehci.0", usb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) orion_clkdev_add(NULL, "orion-ehci.1", usb1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) orion_clkdev_add(NULL, "sata_mv.0", sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) orion_clkdev_add("0", "pcie", pex0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) orion_clkdev_add("1", "pcie", pex1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) orion_clkdev_add(NULL, "orion_nand", nand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) orion_clkdev_add(NULL, "mvebu-audio.0", i2s0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) orion_clkdev_add(NULL, "mvebu-audio.1", i2s1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) orion_clkdev_add(NULL, "mv_crypto", crypto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) orion_clkdev_add(NULL, "dove-ac97", ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) orion_clkdev_add(NULL, "dove-pdma", pdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * EHCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __init dove_ehci0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * EHCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void __init dove_ehci1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * GE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 1600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * SoC RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void __init dove_rtc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __init dove_uart0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IRQ_DOVE_UART_0, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * UART1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __init dove_uart1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IRQ_DOVE_UART_1, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * UART2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __init dove_uart2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IRQ_DOVE_UART_2, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * UART3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __init dove_uart3_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IRQ_DOVE_UART_3, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __init dove_spi0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) orion_spi_init(DOVE_SPI0_PHYS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void __init dove_spi1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __init dove_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Time handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void __init dove_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) orion_time_set_base(TIMER_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mvebu_mbus_init("marvell,dove-mbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int __init dove_find_tclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 166666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __init dove_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dove_tclk = dove_find_tclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IRQ_DOVE_BRIDGE, dove_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * XOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __init dove_xor0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * XOR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void __init dove_xor1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * SDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static u64 sdio_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct resource dove_sdio0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .start = DOVE_SDIO0_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .end = DOVE_SDIO0_PHYS_BASE + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .start = IRQ_DOVE_SDIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .end = IRQ_DOVE_SDIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct platform_device dove_sdio0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "sdhci-dove",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .dma_mask = &sdio_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .resource = dove_sdio0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_resources = ARRAY_SIZE(dove_sdio0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void __init dove_sdio0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) platform_device_register(&dove_sdio0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct resource dove_sdio1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .start = DOVE_SDIO1_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .end = DOVE_SDIO1_PHYS_BASE + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .start = IRQ_DOVE_SDIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .end = IRQ_DOVE_SDIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct platform_device dove_sdio1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "sdhci-dove",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .dma_mask = &sdio_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .resource = dove_sdio1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_resources = ARRAY_SIZE(dove_sdio1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void __init dove_sdio1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) platform_device_register(&dove_sdio1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void __init dove_setup_cpu_wins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * The PCIe windows will no longer be statically allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * here once Dove is migrated to the pci-mvebu driver. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * non-PCIe windows will no longer be created here once Dove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * fully moves to DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DOVE_MBUS_PCIE0_IO_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DOVE_PCIE0_IO_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DOVE_PCIE0_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DOVE_PCIE0_IO_BUS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DOVE_MBUS_PCIE1_IO_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DOVE_PCIE1_IO_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DOVE_PCIE1_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DOVE_PCIE1_IO_BUS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DOVE_MBUS_PCIE0_MEM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DOVE_PCIE0_MEM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DOVE_PCIE0_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DOVE_MBUS_PCIE1_MEM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DOVE_PCIE1_MEM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DOVE_PCIE1_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DOVE_MBUS_CESA_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DOVE_CESA_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DOVE_CESA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DOVE_MBUS_BOOTROM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DOVE_BOOTROM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DOVE_BOOTROM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DOVE_MBUS_SCRATCHPAD_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DOVE_SCRATCHPAD_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DOVE_SCRATCHPAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct resource orion_wdt_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_device orion_wdt_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "orion_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .num_resources = ARRAY_SIZE(orion_wdt_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .resource = orion_wdt_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void __init __maybe_unused orion_wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) platform_device_register(&orion_wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .rst_mask = PMU_SW_RST_VIDEO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .iso_mask = PMU_ISO_VIDEO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "vpu-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .rst_mask = PMU_SW_RST_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .iso_mask = PMU_ISO_GPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "gpu-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct dove_pmu_initdata pmu_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .pmc_base = DOVE_PMU_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .irq = IRQ_DOVE_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .irq_domain_start = IRQ_DOVE_PMU_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .domains = pmu_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __init dove_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (dove_tclk + 499999) / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #ifdef CONFIG_CACHE_TAUROS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tauros2_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dove_setup_cpu_wins();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Setup root of clk tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dove_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* internal devices that every board has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dove_init_pmu_legacy(&pmu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dove_rtc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dove_xor0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dove_xor1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void dove_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Enable soft reset to assert RSTOUTn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Assert soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(SOFT_RESET, SYSTEM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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