Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Mbus-L to Mbus Bridge Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ASM_ARCH_BRIDGE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_BRIDGE_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "dove.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define  CPU_CTRL_PCIE0_LINK	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define  CPU_RESET		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define  CPU_CTRL_PCIE1_LINK	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RSTOUTn_MASK_PHYS	(BRIDGE_PHYS_BASE + 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define  SOFT_RESET_OUT_EN	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define  SOFT_RESET		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE + 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define  BRIDGE_INT_TIMER1_CLR	(~0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IRQ_CAUSE_LOW_OFF	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_MASK_LOW_OFF	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FIQ_MASK_LOW_OFF	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ENDPOINT_MASK_LOW_OFF	0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_CAUSE_HIGH_OFF	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_MASK_HIGH_OFF	0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FIQ_MASK_HIGH_OFF	0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ENDPOINT_MASK_HIGH_OFF	0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_INTERRUPT_MASK_OFF	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_MASK_LOW		(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FIQ_MASK_LOW		(IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ENDPOINT_MASK_LOW	(IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IRQ_MASK_HIGH		(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FIQ_MASK_HIGH		(IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE + 0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif