Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * mach-davinci/sram.c - DaVinci simple SRAM allocator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2009 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static struct gen_pool *sram_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct gen_pool *sram_get_gen_pool(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	return sram_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void *sram_alloc(size_t len, dma_addr_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	dma_addr_t dma_base = davinci_soc_info.sram_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	if (dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		*dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (!sram_pool || (dma && !dma_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	return gen_pool_dma_alloc(sram_pool, len, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EXPORT_SYMBOL(sram_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void sram_free(void *addr, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	gen_pool_free(sram_pool, (unsigned long) addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) EXPORT_SYMBOL(sram_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * REVISIT This supports CPU and DMA access to/from SRAM, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * doesn't (yet?) support some other notable uses of SRAM:  as TCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  * for data and/or instructions; and holding code needed to enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * and exit suspend states (while DRAM can't be used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int __init sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	phys_addr_t phys = davinci_soc_info.sram_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	unsigned len = davinci_soc_info.sram_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		len = min_t(unsigned, len, SRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		if (!sram_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (sram_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		addr = ioremap(phys, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 					   phys, len, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	WARN_ON(status < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) core_initcall(sram_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)