Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TI DaVinci serial driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				    int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	offset <<= p->regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	__raw_writel(value, p->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void __init davinci_serial_reset(struct plat_serial8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned int pwremu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	serial_write_reg(p, UART_IER, 0);  /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	pwremu |= (0x3 << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	pwremu |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	if (cpu_is_davinci_dm646x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		serial_write_reg(p, UART_DM646X_SCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				 UART_DM646X_SCR_TX_WATERMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int __init davinci_serial_init(struct platform_device *serial_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	struct plat_serial8250_port *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	 * Make sure the serial ports are muxed on at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 * You have to mux them off in device drivers later on if not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		dev = &serial_dev[i].dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		p = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		ret = platform_device_register(&serial_dev[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		clk = clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			pr_err("%s:%d: failed to get UART%d clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			       __func__, __LINE__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		p->uartclk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		if (!p->membase && p->mapbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 			p->membase = ioremap(p->mapbase, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 			if (p->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 				p->flags &= ~UPF_IOREMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 				pr_err("uart regs ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 		if (p->membase && p->type != PORT_AR7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 			davinci_serial_reset(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }