Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  DaVinci Power & Sleep Controller (PSC) defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  This program is free software; you can redistribute  it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  under  the terms of  the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Free Software Foundation;  either version 2 of the  License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifndef __ASM_ARCH_PSC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define __ASM_ARCH_PSC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Power and Sleep Controller (PSC) Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DAVINCI_GPSC_ARMDOMAIN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DAVINCI_GPSC_DSPDOMAIN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DAVINCI_LPSC_VPSSMSTR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DAVINCI_LPSC_VPSSSLV		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DAVINCI_LPSC_TPCC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DAVINCI_LPSC_TPTC0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DAVINCI_LPSC_TPTC1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DAVINCI_LPSC_EMAC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DAVINCI_LPSC_EMAC_WRAPPER	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DAVINCI_LPSC_USB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DAVINCI_LPSC_ATA		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DAVINCI_LPSC_VLYNQ		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DAVINCI_LPSC_UHPI		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DAVINCI_LPSC_DDR_EMIF		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DAVINCI_LPSC_AEMIF		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DAVINCI_LPSC_MMC_SD		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DAVINCI_LPSC_McBSP		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DAVINCI_LPSC_I2C		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DAVINCI_LPSC_UART0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DAVINCI_LPSC_UART1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DAVINCI_LPSC_UART2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DAVINCI_LPSC_SPI		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DAVINCI_LPSC_PWM0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DAVINCI_LPSC_PWM1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DAVINCI_LPSC_PWM2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DAVINCI_LPSC_GPIO		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DAVINCI_LPSC_TIMER0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DAVINCI_LPSC_TIMER1		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DAVINCI_LPSC_TIMER2		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DAVINCI_LPSC_SYSTEM_SUBSYS	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DAVINCI_LPSC_ARM		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DAVINCI_LPSC_SCR2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DAVINCI_LPSC_SCR3		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DAVINCI_LPSC_SCR4		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DAVINCI_LPSC_CROSSBAR		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DAVINCI_LPSC_CFG27		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DAVINCI_LPSC_CFG3		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DAVINCI_LPSC_CFG5		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DAVINCI_LPSC_GEM		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DAVINCI_LPSC_IMCOP		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DM355_LPSC_TIMER3		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DM355_LPSC_SPI1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DM355_LPSC_MMC_SD1		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DM355_LPSC_McBSP1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DM355_LPSC_PWM3			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DM355_LPSC_SPI2			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DM355_LPSC_RTO			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DM355_LPSC_VPSS_DAC		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* DM365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DM365_LPSC_TIMER3	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DM365_LPSC_SPI1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DM365_LPSC_MMC_SD1	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DM365_LPSC_McBSP1	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DM365_LPSC_PWM3		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DM365_LPSC_SPI2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DM365_LPSC_RTO		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DM365_LPSC_TIMER4	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DM365_LPSC_SPI0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DM365_LPSC_SPI3		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DM365_LPSC_SPI4		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DM365_LPSC_EMAC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DM365_LPSC_VOICE_CODEC	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DM365_LPSC_DAC_CLK	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DM365_LPSC_VPSSMSTR	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DM365_LPSC_MJCP		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * LPSC Assignments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DM646X_LPSC_ARM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DM646X_LPSC_C64X_CPU	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DM646X_LPSC_HDVICP0	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DM646X_LPSC_HDVICP1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DM646X_LPSC_TPCC	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DM646X_LPSC_TPTC0	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DM646X_LPSC_TPTC1	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DM646X_LPSC_TPTC2	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DM646X_LPSC_TPTC3	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DM646X_LPSC_PCI		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DM646X_LPSC_EMAC	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DM646X_LPSC_VDCE	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DM646X_LPSC_VPSSMSTR	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DM646X_LPSC_VPSSSLV	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DM646X_LPSC_TSIF0	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DM646X_LPSC_TSIF1	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DM646X_LPSC_DDR_EMIF	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DM646X_LPSC_AEMIF	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DM646X_LPSC_McASP0	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DM646X_LPSC_McASP1	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DM646X_LPSC_CRGEN0	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DM646X_LPSC_CRGEN1	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DM646X_LPSC_UART0	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DM646X_LPSC_UART1	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DM646X_LPSC_UART2	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DM646X_LPSC_PWM0	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DM646X_LPSC_PWM1	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DM646X_LPSC_I2C		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DM646X_LPSC_SPI		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DM646X_LPSC_GPIO	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DM646X_LPSC_TIMER0	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DM646X_LPSC_TIMER1	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DM646X_LPSC_ARM_INTC	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* PSC0 defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DA8XX_LPSC0_TPCC		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DA8XX_LPSC0_TPTC0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DA8XX_LPSC0_TPTC1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DA8XX_LPSC0_EMIF25		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DA8XX_LPSC0_SPI0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DA8XX_LPSC0_MMC_SD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DA8XX_LPSC0_AINTC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DA8XX_LPSC0_ARM_RAM_ROM		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DA8XX_LPSC0_SECU_MGR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DA8XX_LPSC0_UART0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DA8XX_LPSC0_SCR0_SS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DA8XX_LPSC0_SCR1_SS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DA8XX_LPSC0_SCR2_SS		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DA8XX_LPSC0_PRUSS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DA8XX_LPSC0_ARM			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DA8XX_LPSC0_GEM			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* PSC1 defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DA850_LPSC1_TPCC1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DA8XX_LPSC1_USB20		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DA8XX_LPSC1_USB11		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DA8XX_LPSC1_GPIO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DA8XX_LPSC1_UHPI		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DA8XX_LPSC1_CPGMAC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DA8XX_LPSC1_EMIF3C		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DA8XX_LPSC1_McASP0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DA830_LPSC1_McASP1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DA850_LPSC1_SATA		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DA830_LPSC1_McASP2		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DA850_LPSC1_VPIF		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DA8XX_LPSC1_SPI1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DA8XX_LPSC1_I2C			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DA8XX_LPSC1_UART1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DA8XX_LPSC1_UART2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DA850_LPSC1_McBSP0		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DA850_LPSC1_McBSP1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DA8XX_LPSC1_LCDC		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DA8XX_LPSC1_PWM			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DA850_LPSC1_MMC_SD1		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DA8XX_LPSC1_ECAP		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DA830_LPSC1_EQEP		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DA850_LPSC1_TPTC2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DA8XX_LPSC1_SCR_P0_SS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DA8XX_LPSC1_SCR_P1_SS		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DA8XX_LPSC1_CR_P3_SS		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DA8XX_LPSC1_L3_CBA_RAM		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PSC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EPCPR		0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PTCMD		0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PTSTAT		0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PDSTAT		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PDCTL		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MDSTAT		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MDCTL		0xA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PSC module states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PSC_STATE_SWRSTDISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PSC_STATE_SYNCRST	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PSC_STATE_DISABLE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PSC_STATE_ENABLE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MDSTAT_STATE_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PDSTAT_STATE_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MDCTL_LRST		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MDCTL_FORCE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PDCTL_NEXT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PDCTL_EPCGOOD		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* __ASM_ARCH_PSC_H */