^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DaVinci Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/da8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "psc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DA850_PLL1_BASE 0x01e1a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DEEPSLEEP_SLEEPCOUNT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void (*davinci_sram_suspend) (struct davinci_pm_config *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct davinci_pm_config pm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .sleepcount = DEEPSLEEP_SLEEPCOUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .ddrpsc_num = DA8XX_LPSC1_EMIF3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void davinci_sram_push(void *dest, void *src, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) memcpy(dest, src, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void davinci_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Switch CPU PLL to bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) udelay(PLL_BYPASS_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Powerdown CPU PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val |= PLLCTL_PLLPWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Configure sleep count in deep sleep register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = __raw_readl(pm_config.deepsleep_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val |= pm_config.sleepcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __raw_writel(val, pm_config.deepsleep_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* System goes to sleep in this call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) davinci_sram_suspend(&pm_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* put CPU PLL in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val &= ~PLLCTL_PLLRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* put CPU PLL in power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val &= ~PLLCTL_PLLPWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* wait for CPU PLL reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) udelay(PLL_RESET_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* bring CPU PLL out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val |= PLLCTL_PLLRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Wait for CPU PLL to lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) udelay(PLL_LOCK_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Remove CPU PLL from bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val &= ~PLLCTL_PLLENSRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val |= PLLCTL_PLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int davinci_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) davinci_pm_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct platform_suspend_ops davinci_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enter = davinci_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .valid = suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int __init davinci_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = davinci_cfg_reg(DA850_RTC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!pm_config.cpupll_reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!pm_config.ddrpll_reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto no_ddrpll_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!pm_config.ddrpsc_reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto no_ddrpsc_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!davinci_sram_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pr_err("PM: cannot allocate SRAM memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto no_sram_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) davinci_cpu_suspend_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) suspend_set_ops(&davinci_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) no_sram_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) iounmap(pm_config.ddrpsc_reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) no_ddrpsc_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) iounmap(pm_config.ddrpll_reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) no_ddrpll_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iounmap(pm_config.cpupll_reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags