^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Utility to set the DAVINCI MUX register from a table in mux.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on linux/arch/arm/plat-omap/mux.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 - 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Written by Tony Lindgren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2007 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2008 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *pinmux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Sets the DAVINCI MUX register based on the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int davinci_cfg_reg(const unsigned long index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static DEFINE_SPINLOCK(mux_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct davinci_soc_info *soc_info = &davinci_soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct mux_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int reg_orig = 0, reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int mask, warn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (WARN_ON(!soc_info->pinmux_pins))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!pinmux_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (WARN_ON(!pinmux_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (index >= soc_info->pinmux_pins_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pr_err("Invalid pin mux index: %lu (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) index, soc_info->pinmux_pins_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dump_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) cfg = &soc_info->pinmux_pins[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (cfg->name == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_err("No entry for the specified index\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Update the mux register in question */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (cfg->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spin_lock_irqsave(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mask = (cfg->mask << cfg->mask_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tmp1 = reg_orig & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = reg_orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tmp2 = (cfg->mode << cfg->mask_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg |= tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (tmp1 != tmp2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writel(reg, pinmux_base + cfg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spin_unlock_irqrestore(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (warn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_DAVINCI_MUX_WARNINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pr_warn("initialized %s\n", cfg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #ifdef CONFIG_DAVINCI_MUX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (cfg->debug || warn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pr_warn("Setting register %s\n", cfg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXPORT_SYMBOL(davinci_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int davinci_cfg_reg_list(const short pins[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int i, error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) for (i = 0; pins[i] >= 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) error = davinci_cfg_reg(pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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