Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * DaVinci interrupt controller definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  This program is free software; you can redistribute  it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  under  the terms of  the GNU General  Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Free Software Foundation;  either version 2 of the  License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifndef __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define __ASM_ARCH_IRQS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DAVINCI_ARM_INTC_BASE 0x01C48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IRQ_VDINT0       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IRQ_VDINT1       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IRQ_VDINT2       2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IRQ_HISTINT      3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IRQ_H3AINT       4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IRQ_PRVUINT      5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IRQ_RSZINT       6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IRQ_VFOCINT      7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IRQ_VENCINT      8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IRQ_ASQINT       9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IRQ_IMXINT       10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IRQ_VLCDINT      11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IRQ_USBINT       12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IRQ_EMACINT      13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IRQ_CCINT0       16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IRQ_CCERRINT     17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IRQ_TCERRINT0    18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IRQ_TCERRINT     19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IRQ_PSCIN        20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IRQ_IDE          22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IRQ_HPIINT       23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IRQ_MBXINT       24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IRQ_MBRINT       25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IRQ_MMCINT       26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IRQ_SDIOINT      27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IRQ_MSINT        28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IRQ_DDRINT       29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IRQ_AEMIFINT     30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IRQ_VLQINT       31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IRQ_TINT0_TINT12 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IRQ_TINT0_TINT34 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IRQ_TINT1_TINT12 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IRQ_TINT1_TINT34 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IRQ_PWMINT0      36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IRQ_PWMINT1      37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IRQ_PWMINT2      38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IRQ_I2C          39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IRQ_UARTINT0     40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IRQ_UARTINT1     41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IRQ_UARTINT2     42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IRQ_SPINT0       43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IRQ_SPINT1       44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IRQ_DSP2ARM0     46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IRQ_DSP2ARM1     47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IRQ_GPIO0        48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IRQ_GPIO1        49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IRQ_GPIO2        50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IRQ_GPIO3        51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IRQ_GPIO4        52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IRQ_GPIO5        53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IRQ_GPIO6        54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IRQ_GPIO7        55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IRQ_GPIOBNK0     56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IRQ_GPIOBNK1     57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IRQ_GPIOBNK2     58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IRQ_GPIOBNK3     59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IRQ_GPIOBNK4     60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IRQ_COMMTX       61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IRQ_COMMRX       62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IRQ_EMUINT       63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DAVINCI_N_AINTC_IRQ	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* DaVinci DM6467-specific Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRQ_DM646X_VP_VERTINT0  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IRQ_DM646X_VP_VERTINT1  1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IRQ_DM646X_VP_VERTINT2  2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IRQ_DM646X_VP_VERTINT3  3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IRQ_DM646X_VP_ERRINT    4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IRQ_DM646X_RESERVED_1   5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IRQ_DM646X_RESERVED_2   6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IRQ_DM646X_WDINT        7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IRQ_DM646X_CRGENINT0    8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IRQ_DM646X_CRGENINT1    9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IRQ_DM646X_TSIFINT0     10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IRQ_DM646X_TSIFINT1     11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IRQ_DM646X_VDCEINT      12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IRQ_DM646X_USBINT       13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IRQ_DM646X_USBDMAINT    14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IRQ_DM646X_PCIINT       15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IRQ_DM646X_TCERRINT2    20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IRQ_DM646X_TCERRINT3    21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IRQ_DM646X_IDE          22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IRQ_DM646X_HPIINT       23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IRQ_DM646X_EMACRXTHINT  24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IRQ_DM646X_EMACRXINT    25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IRQ_DM646X_EMACTXINT    26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IRQ_DM646X_EMACMISCINT  27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IRQ_DM646X_MCASP0TXINT  28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IRQ_DM646X_MCASP0RXINT  29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IRQ_DM646X_MCASP1TXINT  30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IRQ_DM646X_RESERVED_3   31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IRQ_DM646X_VLQINT       38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IRQ_DM646X_UARTINT2     42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IRQ_DM646X_SPINT0       43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IRQ_DM646X_SPINT1       44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IRQ_DM646X_DSP2ARMINT   45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IRQ_DM646X_RESERVED_4   46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IRQ_DM646X_PSCINT       47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IRQ_DM646X_GPIO0        48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IRQ_DM646X_GPIO1        49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IRQ_DM646X_GPIO2        50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IRQ_DM646X_GPIO3        51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IRQ_DM646X_GPIO4        52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IRQ_DM646X_GPIO5        53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IRQ_DM646X_GPIO6        54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IRQ_DM646X_GPIO7        55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IRQ_DM646X_GPIOBNK0     56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IRQ_DM646X_GPIOBNK1     57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IRQ_DM646X_GPIOBNK2     58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IRQ_DM646X_DDRINT       59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IRQ_DM646X_AEMIFINT     60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* DaVinci DM355-specific Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IRQ_DM355_CCDC_VDINT0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IRQ_DM355_CCDC_VDINT1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IRQ_DM355_CCDC_VDINT2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IRQ_DM355_IPIPE_HST	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IRQ_DM355_H3AINT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IRQ_DM355_IPIPE_SDR	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IRQ_DM355_IPIPEIFINT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IRQ_DM355_OSDINT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IRQ_DM355_VENCINT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IRQ_DM355_IMCOPINT	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IRQ_DM355_RTOINT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IRQ_DM355_TINT4		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IRQ_DM355_TINT2_TINT12	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IRQ_DM355_UARTINT2	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IRQ_DM355_TINT5		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IRQ_DM355_TINT2_TINT34	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IRQ_DM355_TINT6		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IRQ_DM355_TINT3_TINT12	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IRQ_DM355_SPINT1_0	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IRQ_DM355_SPINT1_1	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IRQ_DM355_SPINT2_0	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IRQ_DM355_SPINT2_1	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IRQ_DM355_TINT7		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IRQ_DM355_TINT3_TINT34	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IRQ_DM355_SDIOINT0	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IRQ_DM355_MMCINT0	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IRQ_DM355_MSINT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IRQ_DM355_MMCINT1	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IRQ_DM355_PWMINT3	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IRQ_DM355_SDIOINT1	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IRQ_DM355_SPINT0_0	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IRQ_DM355_SPINT0_1	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IRQ_DM355_GPIO0		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IRQ_DM355_GPIO1		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IRQ_DM355_GPIO2		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IRQ_DM355_GPIO3		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IRQ_DM355_GPIO4		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IRQ_DM355_GPIO5		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IRQ_DM355_GPIO6		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IRQ_DM355_GPIO7		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IRQ_DM355_GPIO8		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IRQ_DM355_GPIO9		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IRQ_DM355_GPIOBNK0	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IRQ_DM355_GPIOBNK1	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IRQ_DM355_GPIOBNK2	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IRQ_DM355_GPIOBNK3	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IRQ_DM355_GPIOBNK4	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IRQ_DM355_GPIOBNK5	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IRQ_DM355_GPIOBNK6	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* DaVinci DM365-specific Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IRQ_DM365_INSFINT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IRQ_DM365_IMXINT1	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IRQ_DM365_IMXINT0	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IRQ_DM365_KLD_ARMINT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IRQ_DM365_IMCOPINT	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IRQ_DM365_RTOINT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IRQ_DM365_TINT5		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IRQ_DM365_TINT6		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IRQ_DM365_SPINT2_1	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IRQ_DM365_TINT7		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IRQ_DM365_SDIOINT0	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IRQ_DM365_MMCINT1	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IRQ_DM365_PWMINT3	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IRQ_DM365_RTCINT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IRQ_DM365_SDIOINT1	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IRQ_DM365_SPIINT0_0	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IRQ_DM365_SPIINT3_0	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IRQ_DM365_GPIO0		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IRQ_DM365_GPIO1		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IRQ_DM365_GPIO2		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IRQ_DM365_GPIO3		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IRQ_DM365_GPIO4		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IRQ_DM365_GPIO5		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IRQ_DM365_GPIO6		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IRQ_DM365_GPIO7		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IRQ_DM365_EMAC_RXTHRESH	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IRQ_DM365_EMAC_RXPULSE	53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IRQ_DM365_EMAC_TXPULSE	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IRQ_DM365_EMAC_MISCPULSE 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IRQ_DM365_GPIO12	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IRQ_DM365_GPIO13	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IRQ_DM365_GPIO14	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IRQ_DM365_GPIO15	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IRQ_DM365_ADCINT	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IRQ_DM365_KEYINT	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IRQ_DM365_TCERRINT2	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IRQ_DM365_TCERRINT3	62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IRQ_DM365_EMUINT	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* DA8XX interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IRQ_DA8XX_COMMTX		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IRQ_DA8XX_COMMRX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IRQ_DA8XX_NINT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IRQ_DA8XX_EVTOUT0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IRQ_DA8XX_EVTOUT1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IRQ_DA8XX_EVTOUT2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IRQ_DA8XX_EVTOUT3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IRQ_DA8XX_EVTOUT4		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IRQ_DA8XX_EVTOUT5		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IRQ_DA8XX_EVTOUT6		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IRQ_DA8XX_EVTOUT7		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IRQ_DA8XX_CCINT0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IRQ_DA8XX_CCERRINT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IRQ_DA8XX_TCERRINT0		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IRQ_DA8XX_AEMIFINT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IRQ_DA8XX_I2CINT0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IRQ_DA8XX_MMCSDINT0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IRQ_DA8XX_MMCSDINT1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IRQ_DA8XX_ALLINT0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IRQ_DA8XX_RTC			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IRQ_DA8XX_SPINT0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IRQ_DA8XX_TINT12_0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IRQ_DA8XX_TINT34_0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IRQ_DA8XX_TINT12_1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IRQ_DA8XX_TINT34_1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IRQ_DA8XX_UARTINT0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IRQ_DA8XX_KEYMGRINT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IRQ_DA8XX_SECINT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IRQ_DA8XX_SECKEYERR		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IRQ_DA8XX_CHIPINT0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IRQ_DA8XX_CHIPINT1		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IRQ_DA8XX_CHIPINT2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IRQ_DA8XX_CHIPINT3		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IRQ_DA8XX_TCERRINT1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IRQ_DA8XX_C0_RX_THRESH_PULSE	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IRQ_DA8XX_C0_RX_PULSE		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IRQ_DA8XX_C0_TX_PULSE		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IRQ_DA8XX_C0_MISC_PULSE		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IRQ_DA8XX_C1_RX_THRESH_PULSE	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IRQ_DA8XX_C1_RX_PULSE		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IRQ_DA8XX_C1_TX_PULSE		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IRQ_DA8XX_C1_MISC_PULSE		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IRQ_DA8XX_MEMERR		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IRQ_DA8XX_GPIO0			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IRQ_DA8XX_GPIO1			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IRQ_DA8XX_GPIO2			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IRQ_DA8XX_GPIO3			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IRQ_DA8XX_GPIO4			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IRQ_DA8XX_GPIO5			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IRQ_DA8XX_GPIO6			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IRQ_DA8XX_GPIO7			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IRQ_DA8XX_GPIO8			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IRQ_DA8XX_I2CINT1		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IRQ_DA8XX_LCDINT		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IRQ_DA8XX_UARTINT1		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IRQ_DA8XX_MCASPINT		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IRQ_DA8XX_ALLINT1		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IRQ_DA8XX_SPINT1		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IRQ_DA8XX_UHPI_INT1		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IRQ_DA8XX_USB_INT		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IRQ_DA8XX_IRQN			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IRQ_DA8XX_RWAKEUP		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IRQ_DA8XX_UARTINT2		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IRQ_DA8XX_DFTSSINT		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IRQ_DA8XX_EHRPWM0		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IRQ_DA8XX_EHRPWM0TZ		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IRQ_DA8XX_EHRPWM1		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IRQ_DA8XX_EHRPWM1TZ		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IRQ_DA8XX_ECAP0			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IRQ_DA8XX_ECAP1			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IRQ_DA8XX_ECAP2			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IRQ_DA8XX_ARMCLKSTOPREQ		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* DA830 specific interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IRQ_DA830_MPUERR		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IRQ_DA830_IOPUERR		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IRQ_DA830_BOOTCFGERR		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IRQ_DA830_EHRPWM2		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IRQ_DA830_EHRPWM2TZ		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IRQ_DA830_EQEP0			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IRQ_DA830_EQEP1			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IRQ_DA830_T12CMPINT0_0		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IRQ_DA830_T12CMPINT1_0		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IRQ_DA830_T12CMPINT2_0		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IRQ_DA830_T12CMPINT3_0		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IRQ_DA830_T12CMPINT4_0		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IRQ_DA830_T12CMPINT5_0		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IRQ_DA830_T12CMPINT6_0		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IRQ_DA830_T12CMPINT7_0		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IRQ_DA830_T12CMPINT0_1		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IRQ_DA830_T12CMPINT1_1		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IRQ_DA830_T12CMPINT2_1		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IRQ_DA830_T12CMPINT3_1		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IRQ_DA830_T12CMPINT4_1		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IRQ_DA830_T12CMPINT5_1		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IRQ_DA830_T12CMPINT6_1		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IRQ_DA830_T12CMPINT7_1		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DA830_N_CP_INTC_IRQ		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* DA850 speicific interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IRQ_DA850_MPUADDRERR0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IRQ_DA850_MPUPROTERR0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IRQ_DA850_IOPUADDRERR0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IRQ_DA850_IOPUPROTERR0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IRQ_DA850_IOPUADDRERR1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IRQ_DA850_IOPUPROTERR1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IRQ_DA850_IOPUADDRERR2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IRQ_DA850_IOPUPROTERR2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IRQ_DA850_BOOTCFG_ADDR_ERR	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IRQ_DA850_BOOTCFG_PROT_ERR	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IRQ_DA850_MPUADDRERR1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IRQ_DA850_MPUPROTERR1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IRQ_DA850_IOPUADDRERR3		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IRQ_DA850_IOPUPROTERR3		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IRQ_DA850_IOPUADDRERR4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IRQ_DA850_IOPUPROTERR4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IRQ_DA850_IOPUADDRERR5		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IRQ_DA850_IOPUPROTERR5		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IRQ_DA850_MIOPU_BOOTCFG_ERR	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IRQ_DA850_SATAINT		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IRQ_DA850_TINT12_2		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IRQ_DA850_TINT34_2		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IRQ_DA850_TINTALL_2		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IRQ_DA850_MMCSDINT0_1		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IRQ_DA850_MMCSDINT1_1		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IRQ_DA850_T12CMPINT0_2		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IRQ_DA850_T12CMPINT1_2		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IRQ_DA850_T12CMPINT2_2		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IRQ_DA850_T12CMPINT3_2		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IRQ_DA850_T12CMPINT4_2		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IRQ_DA850_T12CMPINT5_2		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IRQ_DA850_T12CMPINT6_2		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IRQ_DA850_T12CMPINT7_2		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IRQ_DA850_T12CMPINT0_3		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IRQ_DA850_T12CMPINT1_3		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IRQ_DA850_T12CMPINT2_3		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IRQ_DA850_T12CMPINT3_3		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IRQ_DA850_T12CMPINT4_3		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IRQ_DA850_T12CMPINT5_3		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IRQ_DA850_T12CMPINT6_3		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IRQ_DA850_T12CMPINT7_3		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IRQ_DA850_RPIINT		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IRQ_DA850_VPIFINT		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IRQ_DA850_CCINT1		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IRQ_DA850_CCERRINT1		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IRQ_DA850_TCERRINT2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IRQ_DA850_TINT12_3		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IRQ_DA850_TINT34_3		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IRQ_DA850_TINTALL_3		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IRQ_DA850_MCBSP0RINT		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IRQ_DA850_MCBSP0XINT		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IRQ_DA850_MCBSP1RINT		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IRQ_DA850_MCBSP1XINT		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DA850_N_CP_INTC_IRQ		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* da850 currently has the most gpio pins (144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DAVINCI_N_GPIO			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif /* __ASM_ARCH_IRQS_H */