^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM646x chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Hilman, Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) Deep Root Systems, LLC. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip/irq-davinci-aintc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "asp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAVINCI_VPIF_BASE (0x01C12000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BIT_MASK(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) BIT_MASK(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DM646X_EMAC_BASE 0x01c80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DM646X_EMAC_CNTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct emac_platform_data dm646x_emac_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .version = EMAC_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct resource dm646x_emac_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .start = DM646X_EMAC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .end = DM646X_EMAC_BASE + SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct platform_device dm646x_emac_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "davinci_emac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .platform_data = &dm646x_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .num_resources = ARRAY_SIZE(dm646x_emac_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .resource = dm646x_emac_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct resource dm646x_mdio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .start = DM646X_EMAC_MDIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct platform_device dm646x_mdio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "davinci_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .resource = dm646x_mdio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Device specific mux setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * soc description mux mode mode mux dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * reg offset mask mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct mux_config dm646x_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [IRQ_DM646X_VP_VERTINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [IRQ_DM646X_VP_VERTINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [IRQ_DM646X_VP_VERTINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [IRQ_DM646X_VP_VERTINT3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [IRQ_DM646X_VP_ERRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [IRQ_DM646X_RESERVED_1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [IRQ_DM646X_RESERVED_2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [IRQ_DM646X_WDINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [IRQ_DM646X_CRGENINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [IRQ_DM646X_CRGENINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [IRQ_DM646X_TSIFINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [IRQ_DM646X_TSIFINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [IRQ_DM646X_VDCEINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [IRQ_DM646X_USBINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [IRQ_DM646X_USBDMAINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [IRQ_DM646X_PCIINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [IRQ_CCINT0] = 7, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [IRQ_CCERRINT] = 7, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [IRQ_TCERRINT0] = 7, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [IRQ_TCERRINT] = 7, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [IRQ_DM646X_TCERRINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [IRQ_DM646X_TCERRINT3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [IRQ_DM646X_IDE] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [IRQ_DM646X_HPIINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [IRQ_DM646X_EMACRXTHINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [IRQ_DM646X_EMACRXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [IRQ_DM646X_EMACTXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [IRQ_DM646X_EMACMISCINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [IRQ_DM646X_MCASP0TXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [IRQ_DM646X_MCASP0RXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [IRQ_DM646X_RESERVED_3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [IRQ_DM646X_MCASP1TXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [IRQ_TINT0_TINT12] = 7, /* clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [IRQ_TINT0_TINT34] = 7, /* clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [IRQ_TINT1_TINT12] = 7, /* DSP timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [IRQ_TINT1_TINT34] = 7, /* system tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [IRQ_PWMINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [IRQ_PWMINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [IRQ_DM646X_VLQINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [IRQ_I2C] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [IRQ_UARTINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [IRQ_UARTINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [IRQ_DM646X_UARTINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [IRQ_DM646X_SPINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [IRQ_DM646X_SPINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [IRQ_DM646X_DSP2ARMINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [IRQ_DM646X_RESERVED_4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [IRQ_DM646X_PSCINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [IRQ_DM646X_GPIO0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [IRQ_DM646X_GPIO1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [IRQ_DM646X_GPIO2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [IRQ_DM646X_GPIO3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [IRQ_DM646X_GPIO4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [IRQ_DM646X_GPIO5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [IRQ_DM646X_GPIO6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [IRQ_DM646X_GPIO7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [IRQ_DM646X_GPIOBNK0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [IRQ_DM646X_GPIOBNK1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [IRQ_DM646X_GPIOBNK2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [IRQ_DM646X_DDRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [IRQ_DM646X_AEMIFINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [IRQ_COMMTX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [IRQ_COMMRX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [IRQ_EMUINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Four Transfer Controllers on DM646x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static s8 dm646x_queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {3, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {-1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct dma_slave_map dm646x_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct edma_soc_info dm646x_edma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .queue_priority_mapping = dm646x_queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .default_queue = EVENTQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .slave_map = dm646x_edma_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .slavecnt = ARRAY_SIZE(dm646x_edma_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct resource edma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .start = 0x01c00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .end = 0x01c00000 + SZ_64K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .start = 0x01c10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .end = 0x01c10000 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "edma3_tc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .start = 0x01c10400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .end = 0x01c10400 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "edma3_tc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .start = 0x01c10800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .end = 0x01c10800 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "edma3_tc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .start = 0x01c10c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .end = 0x01c10c00 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* not using TC*_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct platform_device_info dm646x_edma_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .res = edma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_res = ARRAY_SIZE(edma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .data = &dm646x_edma_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .size_data = sizeof(dm646x_edma_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct resource dm646x_mcasp0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .start = DAVINCI_DM646X_MCASP0_REG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* DIT mode only, rx is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct resource dm646x_mcasp1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .start = DAVINCI_DM646X_MCASP1_REG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct platform_device dm646x_mcasp0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .resource = dm646x_mcasp0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct platform_device dm646x_mcasp1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .resource = dm646x_mcasp1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct platform_device dm646x_dit_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .name = "spdif-dit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static u64 vpif_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct resource vpif_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .start = DAVINCI_VPIF_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .end = DAVINCI_VPIF_BASE + 0x03ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct platform_device vpif_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "vpif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .dma_mask = &vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .resource = vpif_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_resources = ARRAY_SIZE(vpif_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct resource vpif_display_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct platform_device vpif_display_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "vpif_display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .dma_mask = &vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .resource = vpif_display_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .num_resources = ARRAY_SIZE(vpif_display_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct resource vpif_capture_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_device vpif_capture_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "vpif_capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .dma_mask = &vpif_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .resource = vpif_capture_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .num_resources = ARRAY_SIZE(vpif_capture_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct resource dm646x_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .start = DAVINCI_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ngpio = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int __init dm646x_gpio_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return davinci_gpio_register(dm646x_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ARRAY_SIZE(dm646x_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &dm646x_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct map_desc dm646x_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct davinci_id dm646x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .part_no = 0xb770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .cpu_id = DAVINCI_CPU_ID_DM6467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "dm6467_rev1.x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .variant = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .part_no = 0xb770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .cpu_id = DAVINCI_CPU_ID_DM6467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .name = "dm6467_rev3.x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Bottom half of timer0 is used for clockevent, top half is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct davinci_timer_cfg dm646x_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .mapbase = DAVINCI_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .iotype = UPIO_MEM32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mapbase = DAVINCI_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .iotype = UPIO_MEM32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .mapbase = DAVINCI_UART2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .iotype = UPIO_MEM32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct platform_device dm646x_serial_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .platform_data = dm646x_serial0_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .id = PLAT8250_DEV_PLATFORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .platform_data = dm646x_serial1_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .id = PLAT8250_DEV_PLATFORM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .platform_data = dm646x_serial2_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct davinci_soc_info davinci_soc_info_dm646x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .io_desc = dm646x_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .jtag_id_reg = 0x01c40028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .ids = dm646x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ids_num = ARRAY_SIZE(dm646x_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .pinmux_pins = dm646x_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .emac_pdata = &dm646x_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .sram_dma = 0x10010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .sram_len = SZ_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dm646x_mcasp0_device.dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) platform_device_register(&dm646x_mcasp0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dm646x_mcasp1_device.dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) platform_device_register(&dm646x_mcasp1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) platform_device_register(&dm646x_dit_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void dm646x_setup_vpif(struct vpif_display_config *display_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct vpif_capture_config *capture_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) value &= ~VSCLKDIS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) value &= ~VDD3P3V_VID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) vpif_display_dev.dev.platform_data = display_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) vpif_capture_dev.dev.platform_data = capture_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) platform_device_register(&vpif_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) platform_device_register(&vpif_display_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) platform_device_register(&vpif_capture_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int __init dm646x_init_edma(struct edma_rsv_info *rsv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dm646x_edma_pdata.rsv = rsv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) edma_pdev = platform_device_register_full(&dm646x_edma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return PTR_ERR_OR_ZERO(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void __init dm646x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) davinci_common_init(&davinci_soc_info_dm646x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) davinci_map_sysmod();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void __init dm646x_init_time(unsigned long ref_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned long aux_clkin_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void __iomem *pll1, *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dm646x_pll1_init(NULL, pll1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dm646x_psc_init(NULL, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rv = davinci_timer_register(clk, &dm646x_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static struct resource dm646x_pll2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .start = DAVINCI_PLL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct platform_device dm646x_pll2_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = "dm646x-pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .resource = dm646x_pll2_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void __init dm646x_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* PLL1 and PSC are registered in dm646x_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) platform_device_register(&dm646x_pll2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct davinci_aintc_config dm646x_aintc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .start = DAVINCI_ARM_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .num_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .prios = dm646x_default_priorities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) void __init dm646x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) davinci_aintc_init(&dm646x_aintc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int __init dm646x_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!cpu_is_davinci_dm646x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) platform_device_register(&dm646x_mdio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) platform_device_register(&dm646x_emac_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = davinci_init_wdt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) postcore_initcall(dm646x_init_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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