^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM644x chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Hilman, Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) Deep Root Systems, LLC. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip/irq-davinci-aintc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "asp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Device specific clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DM644X_REF_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DM644X_EMAC_BASE 0x01c80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DM644X_EMAC_CNTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct emac_platform_data dm644x_emac_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .version = EMAC_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct resource dm644x_emac_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .start = DM644X_EMAC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .end = DM644X_EMAC_BASE + SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct platform_device dm644x_emac_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "davinci_emac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .platform_data = &dm644x_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_resources = ARRAY_SIZE(dm644x_emac_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .resource = dm644x_emac_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct resource dm644x_mdio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .start = DM644X_EMAC_MDIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct platform_device dm644x_mdio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "davinci_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .resource = dm644x_mdio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Device specific mux setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * soc description mux mode mode mux dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * reg offset mask mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct mux_config dm644x_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [IRQ_VDINT0] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [IRQ_VDINT1] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [IRQ_VDINT2] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [IRQ_HISTINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [IRQ_H3AINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [IRQ_PRVUINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [IRQ_RSZINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [IRQ_VENCINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [IRQ_ASQINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [IRQ_IMXINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [IRQ_VLCDINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [IRQ_USBINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [IRQ_EMACINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [14] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [15] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [IRQ_CCINT0] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [IRQ_CCERRINT] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [IRQ_TCERRINT0] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [IRQ_TCERRINT] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [IRQ_PSCIN] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [21] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [IRQ_IDE] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [23] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [IRQ_MBXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [IRQ_MBRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [IRQ_MMCINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [IRQ_SDIOINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [28] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [IRQ_DDRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [IRQ_AEMIFINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [IRQ_VLQINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [IRQ_TINT0_TINT12] = 2, /* clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [IRQ_TINT0_TINT34] = 2, /* clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [IRQ_TINT1_TINT12] = 7, /* DSP timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [IRQ_TINT1_TINT34] = 7, /* system tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [IRQ_PWMINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [IRQ_PWMINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [IRQ_PWMINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [IRQ_I2C] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [IRQ_UARTINT0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [IRQ_UARTINT1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [IRQ_UARTINT2] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [IRQ_SPINT0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [IRQ_SPINT1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [45] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [IRQ_DSP2ARM0] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [IRQ_DSP2ARM1] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [IRQ_GPIO0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [IRQ_GPIO1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [IRQ_GPIO2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [IRQ_GPIO3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [IRQ_GPIO4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [IRQ_GPIO5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [IRQ_GPIO6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [IRQ_GPIO7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [IRQ_GPIOBNK0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [IRQ_GPIOBNK1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [IRQ_GPIOBNK2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [IRQ_GPIOBNK3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [IRQ_GPIOBNK4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [IRQ_COMMTX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [IRQ_COMMRX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [IRQ_EMUINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static s8 queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {1, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {-1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct dma_slave_map dm644x_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct edma_soc_info dm644x_edma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .queue_priority_mapping = queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .default_queue = EVENTQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .slave_map = dm644x_edma_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .slavecnt = ARRAY_SIZE(dm644x_edma_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct resource edma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .start = 0x01c00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .end = 0x01c00000 + SZ_64K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .start = 0x01c10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .end = 0x01c10000 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "edma3_tc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .start = 0x01c10400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .end = 0x01c10400 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* not using TC*_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct platform_device_info dm644x_edma_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .res = edma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_res = ARRAY_SIZE(edma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .data = &dm644x_edma_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .size_data = sizeof(dm644x_edma_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct resource dm644x_asp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .start = DAVINCI_ASP0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .start = DAVINCI_DMA_ASP0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .end = DAVINCI_DMA_ASP0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .start = DAVINCI_DMA_ASP0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .end = DAVINCI_DMA_ASP0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_device dm644x_asp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "davinci-mcbsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .num_resources = ARRAY_SIZE(dm644x_asp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .resource = dm644x_asp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DM644X_VPSS_BASE 0x01c73400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct resource dm644x_vpss_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* VPSS Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .start = DM644X_VPSS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .end = DM644X_VPSS_BASE + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct platform_device dm644x_vpss_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .dev.platform_data = "dm644x_vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .resource = dm644x_vpss_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct resource dm644x_vpfe_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct resource dm644x_ccdc_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* CCDC Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .start = 0x01c70400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .end = 0x01c70400 + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct platform_device dm644x_ccdc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "dm644x_ccdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .resource = dm644x_ccdc_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct platform_device dm644x_vpfe_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = CAPTURE_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .resource = dm644x_vpfe_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DM644X_OSD_BASE 0x01c72600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct resource dm644x_osd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .start = DM644X_OSD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .end = DM644X_OSD_BASE + 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct platform_device dm644x_osd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = DM644X_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .num_resources = ARRAY_SIZE(dm644x_osd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .resource = dm644x_osd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DM644X_VENC_BASE 0x01c72400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct resource dm644x_venc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .start = DM644X_VENC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .end = DM644X_VENC_BASE + 0x17f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DM644X_VPSS_VENCLKEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DM644X_VPSS_DACCLKEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int pclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 v = DM644X_VPSS_VENCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case VPBE_ENC_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) v |= DM644X_VPSS_DACCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case VPBE_ENC_DV_TIMINGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (pclock <= 27000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) v |= DM644X_VPSS_DACCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * For HD, use external clock source since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * HD requires higher clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct resource dm644x_v4l2_disp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct platform_device dm644x_vpbe_display = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "vpbe-v4l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .resource = dm644x_v4l2_disp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct venc_platform_data dm644x_venc_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .setup_clock = dm644x_venc_setup_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct platform_device dm644x_venc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = DM644X_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_resources = ARRAY_SIZE(dm644x_venc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .resource = dm644x_venc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .platform_data = &dm644x_venc_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct platform_device dm644x_vpbe_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "vpbe_controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .dma_mask = &dm644x_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct resource dm644_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .start = DAVINCI_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .ngpio = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int __init dm644x_gpio_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return davinci_gpio_register(dm644_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ARRAY_SIZE(dm644_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &dm644_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct map_desc dm644x_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct davinci_id dm644x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .part_no = 0xb700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .cpu_id = DAVINCI_CPU_ID_DM6446,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .name = "dm6446",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .variant = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .part_no = 0xb700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .cpu_id = DAVINCI_CPU_ID_DM6446,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .name = "dm6446a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Bottom half of timer0 is used for clockevent, top half is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct davinci_timer_cfg dm644x_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .mapbase = DAVINCI_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .mapbase = DAVINCI_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .mapbase = DAVINCI_UART2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct platform_device dm644x_serial_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .platform_data = dm644x_serial0_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .id = PLAT8250_DEV_PLATFORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .platform_data = dm644x_serial1_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .id = PLAT8250_DEV_PLATFORM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .platform_data = dm644x_serial2_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct davinci_soc_info davinci_soc_info_dm644x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .io_desc = dm644x_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .jtag_id_reg = 0x01c40028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .ids = dm644x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .ids_num = ARRAY_SIZE(dm644x_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .pinmux_pins = dm644x_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .emac_pdata = &dm644x_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .sram_dma = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .sram_len = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) void __init dm644x_init_asp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) davinci_cfg_reg(DM644X_MCBSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) platform_device_register(&dm644x_asp_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) void __init dm644x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) davinci_common_init(&davinci_soc_info_dm644x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) davinci_map_sysmod();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void __init dm644x_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void __iomem *pll1, *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dm644x_pll1_init(NULL, pll1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dm644x_psc_init(NULL, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rv = davinci_timer_register(clk, &dm644x_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct resource dm644x_pll2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .start = DAVINCI_PLL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static struct platform_device dm644x_pll2_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .name = "dm644x-pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .resource = dm644x_pll2_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) void __init dm644x_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* PLL1 and PSC are registered in dm644x_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) platform_device_register(&dm644x_pll2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct vpbe_config *vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (vpfe_cfg || vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) platform_device_register(&dm644x_vpss_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (vpfe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) platform_device_register(&dm644x_ccdc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) platform_device_register(&dm644x_vpfe_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (vpbe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) platform_device_register(&dm644x_osd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) platform_device_register(&dm644x_venc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) platform_device_register(&dm644x_vpbe_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) platform_device_register(&dm644x_vpbe_display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct davinci_aintc_config dm644x_aintc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .start = DAVINCI_ARM_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .num_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .prios = dm644x_default_priorities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) void __init dm644x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) davinci_aintc_init(&dm644x_aintc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void __init dm644x_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) edma_pdev = platform_device_register_full(&dm644x_edma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (IS_ERR(edma_pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pr_warn("%s: Failed to register eDMA\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) platform_device_register(&dm644x_mdio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) platform_device_register(&dm644x_emac_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = davinci_init_wdt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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