^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM365 chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip/irq-davinci-aintc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/keyscan-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/spi-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "asp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DM365_RTC_BASE 0x01c69000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DM365_KEYSCAN_BASE 0x01c69400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DM365_OSD_BASE 0x01c71c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DM365_VENC_BASE 0x01c71e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAVINCI_DM365_VC_BASE 0x01d0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DAVINCI_DMA_VC_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DAVINCI_DMA_VC_RX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DM365_EMAC_BASE 0x01d07000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DM365_EMAC_CNTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INTMUX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EVTMUX 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct mux_config dm365_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct davinci_spi_platform_data dm365_spi0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .version = SPI_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .num_chipselect = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .dma_event_q = EVENTQ_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .prescaler_limit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct resource dm365_spi0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .start = 0x01c66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .end = 0x01c667ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct platform_device dm365_spi0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "spi_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .dma_mask = &dm365_spi0_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .platform_data = &dm365_spi0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_resources = ARRAY_SIZE(dm365_spi0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .resource = dm365_spi0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void __init dm365_init_spi0(unsigned chipselect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const struct spi_board_info *info, unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) davinci_cfg_reg(DM365_SPI0_SCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) davinci_cfg_reg(DM365_SPI0_SDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) davinci_cfg_reg(DM365_SPI0_SDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* not all slaves will be wired up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (chipselect_mask & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) davinci_cfg_reg(DM365_SPI0_SDENA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (chipselect_mask & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) davinci_cfg_reg(DM365_SPI0_SDENA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spi_register_board_info(info, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) platform_device_register(&dm365_spi0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct resource dm365_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .start = DAVINCI_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .ngpio = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .gpio_unbanked = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int __init dm365_gpio_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return davinci_gpio_register(dm365_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ARRAY_SIZE(dm365_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &dm365_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct emac_platform_data dm365_emac_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .version = EMAC_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct resource dm365_emac_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .start = DM365_EMAC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .end = DM365_EMAC_BASE + SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct platform_device dm365_emac_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "davinci_emac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .platform_data = &dm365_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .num_resources = ARRAY_SIZE(dm365_emac_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .resource = dm365_emac_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct resource dm365_mdio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .start = DM365_EMAC_MDIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct platform_device dm365_mdio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "davinci_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_resources = ARRAY_SIZE(dm365_mdio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .resource = dm365_mdio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [IRQ_VDINT0] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [IRQ_VDINT1] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [IRQ_VDINT2] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [IRQ_HISTINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [IRQ_H3AINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [IRQ_PRVUINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [IRQ_RSZINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [IRQ_DM365_INSFINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [IRQ_VENCINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [IRQ_ASQINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [IRQ_IMXINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [IRQ_DM365_IMCOPINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [IRQ_USBINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [IRQ_DM365_RTOINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [IRQ_DM365_TINT5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [IRQ_DM365_TINT6] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [IRQ_CCINT0] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [IRQ_CCERRINT] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [IRQ_TCERRINT0] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [IRQ_TCERRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [IRQ_PSCIN] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [IRQ_DM365_SPINT2_1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [IRQ_DM365_TINT7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [IRQ_DM365_SDIOINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [IRQ_MBXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [IRQ_MBRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [IRQ_MMCINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [IRQ_DM365_MMCINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [IRQ_DM365_PWMINT3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [IRQ_AEMIFINT] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [IRQ_DM365_SDIOINT1] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [IRQ_TINT0_TINT12] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [IRQ_TINT0_TINT34] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [IRQ_TINT1_TINT12] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [IRQ_TINT1_TINT34] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [IRQ_PWMINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [IRQ_PWMINT1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [IRQ_PWMINT2] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [IRQ_I2C] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [IRQ_UARTINT0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [IRQ_UARTINT1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [IRQ_DM365_RTCINT] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [IRQ_DM365_SPIINT0_0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [IRQ_DM365_SPIINT3_0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [IRQ_DM365_GPIO0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [IRQ_DM365_GPIO1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [IRQ_DM365_GPIO2] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [IRQ_DM365_GPIO3] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [IRQ_DM365_GPIO4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [IRQ_DM365_GPIO5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [IRQ_DM365_GPIO6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [IRQ_DM365_GPIO7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [IRQ_DM365_EMAC_RXTHRESH] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [IRQ_DM365_EMAC_RXPULSE] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [IRQ_DM365_EMAC_TXPULSE] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [IRQ_DM365_EMAC_MISCPULSE] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [IRQ_DM365_GPIO12] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [IRQ_DM365_GPIO13] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [IRQ_DM365_GPIO14] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [IRQ_DM365_GPIO15] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [IRQ_DM365_KEYINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [IRQ_DM365_TCERRINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [IRQ_DM365_TCERRINT3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [IRQ_DM365_EMUINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Four Transfer Controllers on DM365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static s8 dm365_queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {1, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {2, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {3, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {-1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct dma_slave_map dm365_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct edma_soc_info dm365_edma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .queue_priority_mapping = dm365_queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .default_queue = EVENTQ_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .slave_map = dm365_edma_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .slavecnt = ARRAY_SIZE(dm365_edma_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct resource edma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .start = 0x01c00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .end = 0x01c00000 + SZ_64K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .start = 0x01c10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .end = 0x01c10000 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "edma3_tc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .start = 0x01c10400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .end = 0x01c10400 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "edma3_tc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .start = 0x01c10800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .end = 0x01c10800 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "edma3_tc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .start = 0x01c10c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .end = 0x01c10c00 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* not using TC*_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct platform_device_info dm365_edma_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .res = edma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .num_res = ARRAY_SIZE(edma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .data = &dm365_edma_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .size_data = sizeof(dm365_edma_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct resource dm365_asp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .start = DAVINCI_DM365_ASP0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .start = DAVINCI_DMA_ASP0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .end = DAVINCI_DMA_ASP0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .start = DAVINCI_DMA_ASP0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .end = DAVINCI_DMA_ASP0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct platform_device dm365_asp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = "davinci-mcbsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .num_resources = ARRAY_SIZE(dm365_asp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .resource = dm365_asp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct resource dm365_vc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .start = DAVINCI_DM365_VC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .start = DAVINCI_DMA_VC_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .end = DAVINCI_DMA_VC_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .start = DAVINCI_DMA_VC_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .end = DAVINCI_DMA_VC_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct platform_device dm365_vc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .name = "davinci_voicecodec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .num_resources = ARRAY_SIZE(dm365_vc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .resource = dm365_vc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct resource dm365_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .start = DM365_RTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .end = DM365_RTC_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct platform_device dm365_rtc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .name = "rtc_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .num_resources = ARRAY_SIZE(dm365_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .resource = dm365_rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static struct map_desc dm365_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct resource dm365_ks_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .start = DM365_KEYSCAN_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct platform_device dm365_ks_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "davinci_keyscan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .num_resources = ARRAY_SIZE(dm365_ks_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .resource = dm365_ks_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct davinci_id dm365_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .part_no = 0xb83e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .cpu_id = DAVINCI_CPU_ID_DM365,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .name = "dm365_rev1.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .variant = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .part_no = 0xb83e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .manufacturer = 0x017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .cpu_id = DAVINCI_CPU_ID_DM365,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .name = "dm365_rev1.2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * Bottom half of timer0 is used for clockevent, top half is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct davinci_timer_cfg dm365_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DM365_UART1_BASE (IO_PHYS + 0x106000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static struct plat_serial8250_port dm365_serial0_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .mapbase = DAVINCI_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static struct plat_serial8250_port dm365_serial1_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .mapbase = DM365_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct platform_device dm365_serial_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .platform_data = dm365_serial0_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .id = PLAT8250_DEV_PLATFORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .platform_data = dm365_serial1_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct davinci_soc_info davinci_soc_info_dm365 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .io_desc = dm365_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .io_desc_num = ARRAY_SIZE(dm365_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .jtag_id_reg = 0x01c40028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .ids = dm365_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .ids_num = ARRAY_SIZE(dm365_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .pinmux_pins = dm365_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .emac_pdata = &dm365_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .sram_dma = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .sram_len = SZ_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) void __init dm365_init_asp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) davinci_cfg_reg(DM365_MCBSP0_BDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) davinci_cfg_reg(DM365_MCBSP0_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) davinci_cfg_reg(DM365_MCBSP0_BFSX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) davinci_cfg_reg(DM365_MCBSP0_BDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) davinci_cfg_reg(DM365_MCBSP0_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) davinci_cfg_reg(DM365_MCBSP0_BFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) davinci_cfg_reg(DM365_EVT2_ASP_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) davinci_cfg_reg(DM365_EVT3_ASP_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) platform_device_register(&dm365_asp_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void __init dm365_init_vc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) davinci_cfg_reg(DM365_EVT2_VC_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) davinci_cfg_reg(DM365_EVT3_VC_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) platform_device_register(&dm365_vc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dm365_ks_device.dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) platform_device_register(&dm365_ks_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) void __init dm365_init_rtc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) davinci_cfg_reg(DM365_INT_PRTCSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) platform_device_register(&dm365_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void __init dm365_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) davinci_common_init(&davinci_soc_info_dm365);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) davinci_map_sysmod();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) void __init dm365_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void __iomem *pll1, *pll2, *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dm365_pll1_init(NULL, pll1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dm365_pll2_init(NULL, pll2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dm365_psc_init(NULL, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) rv = davinci_timer_register(clk, &dm365_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) void __init dm365_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* all clocks are currently registered in dm365_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct resource dm365_vpss_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* VPSS ISP5 Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .name = "isp5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .start = 0x01c70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .end = 0x01c70000 + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* VPSS CLK Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .start = 0x01c70200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .end = 0x01c70200 + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static struct platform_device dm365_vpss_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .dev.platform_data = "dm365_vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .num_resources = ARRAY_SIZE(dm365_vpss_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .resource = dm365_vpss_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct resource vpfe_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static struct platform_device vpfe_capture_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .name = CAPTURE_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .num_resources = ARRAY_SIZE(vpfe_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .resource = vpfe_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void dm365_isif_setup_pinmux(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) davinci_cfg_reg(DM365_VIN_CAM_WEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) davinci_cfg_reg(DM365_VIN_CAM_VD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) davinci_cfg_reg(DM365_VIN_CAM_HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct resource isif_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* ISIF Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .start = 0x01c71000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .end = 0x01c71000 + 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* ISIF Linearization table 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .start = 0x1C7C000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .end = 0x1C7C000 + 0x2ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* ISIF Linearization table 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .start = 0x1C7C400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .end = 0x1C7C400 + 0x2ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct platform_device dm365_isif_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "isif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .num_resources = ARRAY_SIZE(isif_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .resource = isif_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .platform_data = dm365_isif_setup_pinmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static struct resource dm365_osd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .start = DM365_OSD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .end = DM365_OSD_BASE + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct platform_device dm365_osd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = DM365_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .num_resources = ARRAY_SIZE(dm365_osd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .resource = dm365_osd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .dma_mask = &dm365_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static struct resource dm365_venc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* venc registers io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .start = DM365_VENC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .end = DM365_VENC_BASE + 0x177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* vdaccfg registers io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct resource dm365_v4l2_disp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* venc registers io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .start = DM365_VENC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .end = DM365_VENC_BASE + 0x177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) switch (if_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case MEDIA_BUS_FMT_SGRBG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) davinci_cfg_reg(DM365_VOUT_FIELD_G81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) davinci_cfg_reg(DM365_VOUT_COUTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) davinci_cfg_reg(DM365_VOUT_COUTH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case MEDIA_BUS_FMT_YUYV10_1X20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) davinci_cfg_reg(DM365_VOUT_FIELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) davinci_cfg_reg(DM365_VOUT_FIELD_G81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) davinci_cfg_reg(DM365_VOUT_COUTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) davinci_cfg_reg(DM365_VOUT_COUTH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned int pclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) void __iomem *vpss_clkctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case VPBE_ENC_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case VPBE_ENC_DV_TIMINGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (pclock <= 27000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* set sysclk4 to output 74.25 MHz from pll1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) VPSS_VENCCLKEN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) writel(val, vpss_clkctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static struct platform_device dm365_vpbe_display = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "vpbe-v4l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .resource = dm365_v4l2_disp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .dma_mask = &dm365_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static struct venc_platform_data dm365_venc_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .setup_pinmux = dm365_vpbe_setup_pinmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .setup_clock = dm365_venc_setup_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static struct platform_device dm365_venc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .name = DM365_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .num_resources = ARRAY_SIZE(dm365_venc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .resource = dm365_venc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .dma_mask = &dm365_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .platform_data = (void *)&dm365_venc_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct platform_device dm365_vpbe_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .name = "vpbe_controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .dma_mask = &dm365_video_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct vpbe_config *vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (vpfe_cfg || vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) platform_device_register(&dm365_vpss_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (vpfe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) vpfe_capture_dev.dev.platform_data = vpfe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) platform_device_register(&dm365_isif_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) platform_device_register(&vpfe_capture_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (vpbe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) platform_device_register(&dm365_osd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) platform_device_register(&dm365_venc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) platform_device_register(&dm365_vpbe_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) platform_device_register(&dm365_vpbe_display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const struct davinci_aintc_config dm365_aintc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .start = DAVINCI_ARM_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .num_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .prios = dm365_default_priorities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) void __init dm365_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) davinci_aintc_init(&dm365_aintc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int __init dm365_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!cpu_is_davinci_dm365())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) davinci_cfg_reg(DM365_INT_EDMA_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) edma_pdev = platform_device_register_full(&dm365_edma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (IS_ERR(edma_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pr_warn("%s: Failed to register eDMA\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return PTR_ERR(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) platform_device_register(&dm365_mdio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) platform_device_register(&dm365_emac_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = davinci_init_wdt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) postcore_initcall(dm365_init_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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