^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI DaVinci DM355 chip specific setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Kevin Hilman, Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2007 (c) Deep Root Systems, LLC. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip/irq-davinci-aintc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_data/spi-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mach/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <clocksource/timer-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "asp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "davinci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DM355_UART2_BASE (IO_PHYS + 0x206000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DM355_OSD_BASE (IO_PHYS + 0x70200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DM355_VENC_BASE (IO_PHYS + 0x70400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Device specific clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct resource dm355_spi0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .start = 0x01c66000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .end = 0x01c667ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct davinci_spi_platform_data dm355_spi0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .version = SPI_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .num_chipselect = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .cshold_bug = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .dma_event_q = EVENTQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .prescaler_limit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct platform_device dm355_spi0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "spi_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .dma_mask = &dm355_spi0_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .platform_data = &dm355_spi0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .num_resources = ARRAY_SIZE(dm355_spi0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .resource = dm355_spi0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __init dm355_init_spi0(unsigned chipselect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct spi_board_info *info, unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* for now, assume we need MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) davinci_cfg_reg(DM355_SPI0_SDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* not all slaves will be wired up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (chipselect_mask & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) davinci_cfg_reg(DM355_SPI0_SDENA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (chipselect_mask & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) davinci_cfg_reg(DM355_SPI0_SDENA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spi_register_board_info(info, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) platform_device_register(&dm355_spi0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INTMUX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EVTMUX 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Device specific mux setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * soc description mux mode mode mux dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * reg offset mask mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct mux_config dm355_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_DAVINCI_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [IRQ_DM355_CCDC_VDINT0] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [IRQ_DM355_CCDC_VDINT1] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [IRQ_DM355_CCDC_VDINT2] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [IRQ_DM355_IPIPE_HST] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [IRQ_DM355_H3AINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [IRQ_DM355_IPIPE_SDR] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [IRQ_DM355_IPIPEIFINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [IRQ_DM355_OSDINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [IRQ_DM355_VENCINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [IRQ_ASQINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [IRQ_IMXINT] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [IRQ_USBINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [IRQ_DM355_RTOINT] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [IRQ_DM355_UARTINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [IRQ_DM355_TINT6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [IRQ_CCINT0] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [IRQ_CCERRINT] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [IRQ_TCERRINT0] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [IRQ_TCERRINT] = 5, /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [IRQ_DM355_SPINT2_1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [IRQ_DM355_TINT7] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [IRQ_DM355_SDIOINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [IRQ_MBXINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [IRQ_MBRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [IRQ_MMCINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [IRQ_DM355_MMCINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [IRQ_DM355_PWMINT3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [IRQ_DDRINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [IRQ_AEMIFINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [IRQ_DM355_SDIOINT1] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [IRQ_TINT0_TINT12] = 2, /* clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [IRQ_TINT0_TINT34] = 2, /* clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [IRQ_TINT1_TINT12] = 7, /* DSP timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [IRQ_TINT1_TINT34] = 7, /* system tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [IRQ_PWMINT0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [IRQ_PWMINT1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [IRQ_PWMINT2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [IRQ_I2C] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [IRQ_UARTINT0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [IRQ_UARTINT1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [IRQ_DM355_SPINT0_0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [IRQ_DM355_SPINT0_1] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [IRQ_DM355_GPIO0] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [IRQ_DM355_GPIO1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [IRQ_DM355_GPIO2] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [IRQ_DM355_GPIO3] = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [IRQ_DM355_GPIO4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [IRQ_DM355_GPIO5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [IRQ_DM355_GPIO6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [IRQ_DM355_GPIO7] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [IRQ_DM355_GPIO8] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [IRQ_DM355_GPIO9] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [IRQ_DM355_GPIOBNK0] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [IRQ_DM355_GPIOBNK1] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [IRQ_DM355_GPIOBNK2] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [IRQ_DM355_GPIOBNK3] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [IRQ_DM355_GPIOBNK4] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [IRQ_DM355_GPIOBNK5] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [IRQ_DM355_GPIOBNK6] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [IRQ_COMMTX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [IRQ_COMMRX] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [IRQ_EMUINT] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static s8 queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {1, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {-1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct dma_slave_map dm355_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct edma_soc_info dm355_edma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .queue_priority_mapping = queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .default_queue = EVENTQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .slave_map = dm355_edma_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .slavecnt = ARRAY_SIZE(dm355_edma_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct resource edma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .start = 0x01c00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .end = 0x01c00000 + SZ_64K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .start = 0x01c10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .end = 0x01c10000 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "edma3_tc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .start = 0x01c10400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .end = 0x01c10400 + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* not using (or muxing) TC*_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct platform_device_info dm355_edma_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .res = edma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .num_res = ARRAY_SIZE(edma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .data = &dm355_edma_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .size_data = sizeof(dm355_edma_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct resource dm355_asp1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .start = DAVINCI_ASP1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .start = DAVINCI_DMA_ASP1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .end = DAVINCI_DMA_ASP1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .start = DAVINCI_DMA_ASP1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .end = DAVINCI_DMA_ASP1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct platform_device dm355_asp1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "davinci-mcbsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_resources = ARRAY_SIZE(dm355_asp1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .resource = dm355_asp1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void dm355_ccdc_setup_pinmux(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) davinci_cfg_reg(DM355_VIN_PCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) davinci_cfg_reg(DM355_VIN_CAM_WEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) davinci_cfg_reg(DM355_VIN_CAM_VD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) davinci_cfg_reg(DM355_VIN_CAM_HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) davinci_cfg_reg(DM355_VIN_YIN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) davinci_cfg_reg(DM355_VIN_CINL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) davinci_cfg_reg(DM355_VIN_CINH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct resource dm355_vpss_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* VPSS BL Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .start = 0x01c70800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .end = 0x01c70800 + 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* VPSS CLK Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .start = 0x01c70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .end = 0x01c70000 + 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct platform_device dm355_vpss_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .dev.platform_data = "dm355_vpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .num_resources = ARRAY_SIZE(dm355_vpss_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .resource = dm355_vpss_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct resource vpfe_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct resource dm355_ccdc_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* CCDC Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .start = 0x01c70600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .end = 0x01c70600 + 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_device dm355_ccdc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "dm355_ccdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .resource = dm355_ccdc_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .platform_data = dm355_ccdc_setup_pinmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct platform_device vpfe_capture_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = CAPTURE_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .num_resources = ARRAY_SIZE(vpfe_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .resource = vpfe_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct resource dm355_osd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .start = DM355_OSD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .end = DM355_OSD_BASE + 0x17f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct platform_device dm355_osd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = DM355_VPBE_OSD_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .num_resources = ARRAY_SIZE(dm355_osd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .resource = dm355_osd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct resource dm355_venc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* venc registers io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .start = DM355_VENC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .end = DM355_VENC_BASE + 0x17f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* VDAC config register io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct resource dm355_v4l2_disp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* venc registers io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .start = DM355_VENC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .end = DM355_VENC_BASE + 0x17f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (if_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case MEDIA_BUS_FMT_SGRBG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) davinci_cfg_reg(DM355_VOUT_FIELD_G70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case MEDIA_BUS_FMT_YUYV10_1X20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) davinci_cfg_reg(DM355_VOUT_FIELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) davinci_cfg_reg(DM355_VOUT_FIELD_G70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) davinci_cfg_reg(DM355_VOUT_COUTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) davinci_cfg_reg(DM355_VOUT_COUTH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int pclock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void __iomem *vpss_clk_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case VPBE_ENC_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) vpss_clk_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case VPBE_ENC_DV_TIMINGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (pclock > 27000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * For HD, use external clock source since we cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * support HD mode with internal clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct platform_device dm355_vpbe_display = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .name = "vpbe-v4l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .resource = dm355_v4l2_disp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct venc_platform_data dm355_venc_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .setup_pinmux = dm355_vpbe_setup_pinmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .setup_clock = dm355_venc_setup_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct platform_device dm355_venc_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = DM355_VPBE_VENC_SUBDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .num_resources = ARRAY_SIZE(dm355_venc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .resource = dm355_venc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .platform_data = (void *)&dm355_venc_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct platform_device dm355_vpbe_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "vpbe_controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .dma_mask = &vpfe_capture_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct resource dm355_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .start = DAVINCI_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .no_auto_base = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .ngpio = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int __init dm355_gpio_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return davinci_gpio_register(dm355_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ARRAY_SIZE(dm355_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &dm355_gpio_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct map_desc dm355_io_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .virtual = IO_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .pfn = __phys_to_pfn(IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .length = IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Contents of JTAG ID register used to identify exact cpu type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static struct davinci_id dm355_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .variant = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .part_no = 0xb73b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .manufacturer = 0x00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .cpu_id = DAVINCI_CPU_ID_DM355,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .name = "dm355",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Bottom half of timer0 is used for clockevent, top half is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const struct davinci_timer_cfg dm355_timer_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static struct plat_serial8250_port dm355_serial0_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .mapbase = DAVINCI_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static struct plat_serial8250_port dm355_serial1_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .mapbase = DAVINCI_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct plat_serial8250_port dm355_serial2_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .mapbase = DM355_UART2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct platform_device dm355_serial_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .platform_data = dm355_serial0_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .id = PLAT8250_DEV_PLATFORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .platform_data = dm355_serial1_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .id = PLAT8250_DEV_PLATFORM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .platform_data = dm355_serial2_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct davinci_soc_info davinci_soc_info_dm355 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .io_desc = dm355_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .io_desc_num = ARRAY_SIZE(dm355_io_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .jtag_id_reg = 0x01c40028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .ids = dm355_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .ids_num = ARRAY_SIZE(dm355_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .pinmux_pins = dm355_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .sram_dma = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .sram_len = SZ_32K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void __init dm355_init_asp1(u32 evt_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* we don't use ASP1 IRQs, or we'd need to mux them ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (evt_enable & ASP1_TX_EVT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) davinci_cfg_reg(DM355_EVT8_ASP1_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (evt_enable & ASP1_RX_EVT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) davinci_cfg_reg(DM355_EVT9_ASP1_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) platform_device_register(&dm355_asp1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __init dm355_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) davinci_common_init(&davinci_soc_info_dm355);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) davinci_map_sysmod();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void __init dm355_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) void __iomem *pll1, *psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dm355_pll1_init(NULL, pll1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dm355_psc_init(NULL, psc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk = clk_get(NULL, "timer0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (WARN_ON(IS_ERR(clk))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pr_err("Unable to get the timer clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rv = davinci_timer_register(clk, &dm355_timer_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) WARN(rv, "Unable to register the timer: %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static struct resource dm355_pll2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .start = DAVINCI_PLL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static struct platform_device dm355_pll2_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .name = "dm355-pll2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .resource = dm355_pll2_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .num_resources = ARRAY_SIZE(dm355_pll2_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) void __init dm355_register_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* PLL1 and PSC are registered in dm355_init_time() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) platform_device_register(&dm355_pll2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct vpbe_config *vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (vpfe_cfg || vpbe_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) platform_device_register(&dm355_vpss_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (vpfe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) vpfe_capture_dev.dev.platform_data = vpfe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) platform_device_register(&dm355_ccdc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) platform_device_register(&vpfe_capture_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (vpbe_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) platform_device_register(&dm355_osd_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) platform_device_register(&dm355_venc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) platform_device_register(&dm355_vpbe_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) platform_device_register(&dm355_vpbe_display);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct davinci_aintc_config dm355_aintc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .start = DAVINCI_ARM_INTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .num_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .prios = dm355_default_priorities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void __init dm355_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) davinci_aintc_init(&dm355_aintc_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int __init dm355_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!cpu_is_davinci_dm355())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) davinci_cfg_reg(DM355_INT_EDMA_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) edma_pdev = platform_device_register_full(&dm355_edma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (IS_ERR(edma_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pr_warn("%s: Failed to register eDMA\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return PTR_ERR(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = davinci_init_wdt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) postcore_initcall(dm355_init_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags