^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DA8XX/OMAP L1XX platform device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Derived from code that was:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ahci_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <mach/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/da8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "asp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cpuidle.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DA8XX_TPCC_BASE 0x01c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DA8XX_TPTC0_BASE 0x01c08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DA8XX_TPTC1_BASE 0x01c08400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DA8XX_I2C0_BASE 0x01c22000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DA8XX_RTC_BASE 0x01c23000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DA8XX_PRUSS_MEM_BASE 0x01c30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DA8XX_MMCSD0_BASE 0x01c40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DA8XX_SPI0_BASE 0x01c41000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DA830_SPI1_BASE 0x01e12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DA8XX_LCD_CNTRL_BASE 0x01e13000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DA850_SATA_BASE 0x01e18000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DA850_MMCSD1_BASE 0x01e1b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DA8XX_EMAC_MDIO_BASE 0x01e24000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DA8XX_I2C1_BASE 0x01e28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DA850_TPCC1_BASE 0x01e30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DA850_TPTC2_BASE 0x01e38000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DA850_SPI1_BASE 0x01f0e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DA8XX_DDR2_CTL_BASE 0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DA8XX_EMAC_RAM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *da8xx_syscfg0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void __iomem *da8xx_syscfg1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct plat_serial8250_port da8xx_serial0_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .mapbase = DA8XX_UART0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct plat_serial8250_port da8xx_serial1_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .mapbase = DA8XX_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct plat_serial8250_port da8xx_serial2_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .mapbase = DA8XX_UART2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) UPF_IOREMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct platform_device da8xx_serial_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .platform_data = da8xx_serial0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .id = PLAT8250_DEV_PLATFORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .platform_data = da8xx_serial1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .id = PLAT8250_DEV_PLATFORM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .platform_data = da8xx_serial2_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static s8 da8xx_queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {1, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {-1, -1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static s8 da850_queue_priority_mapping[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* {event queue no, Priority} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {-1, -1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct edma_soc_info da8xx_edma0_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .queue_priority_mapping = da8xx_queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .default_queue = EVENTQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct edma_soc_info da850_edma1_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .queue_priority_mapping = da850_queue_priority_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .default_queue = EVENTQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct resource da8xx_edma0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .start = DA8XX_TPCC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .end = DA8XX_TPCC_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .start = DA8XX_TPTC0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "edma3_tc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .start = DA8XX_TPTC1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct resource da850_edma1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "edma3_cc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .start = DA850_TPCC1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .end = DA850_TPCC1_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "edma3_tc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .start = DA850_TPTC2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .end = DA850_TPTC2_BASE + SZ_1K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .name = "edma3_ccint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "edma3_ccerrint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct platform_device_info da8xx_edma0_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .res = da8xx_edma0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .num_res = ARRAY_SIZE(da8xx_edma0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .data = &da8xx_edma0_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .size_data = sizeof(da8xx_edma0_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct platform_device_info da850_edma1_device __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .res = da850_edma1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .num_res = ARRAY_SIZE(da850_edma1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .data = &da850_edma1_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .size_data = sizeof(da850_edma1_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct dma_slave_map da830_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int __init da830_register_edma(struct edma_rsv_info *rsv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) da8xx_edma0_pdata.rsv = rsv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) da8xx_edma0_pdata.slave_map = da830_edma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) edma_pdev = platform_device_register_full(&da8xx_edma0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PTR_ERR_OR_ZERO(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct dma_slave_map da850_edma0_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct dma_slave_map da850_edma1_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int __init da850_register_edma(struct edma_rsv_info *rsv[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct platform_device *edma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (rsv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) da8xx_edma0_pdata.rsv = rsv[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) da850_edma1_pdata.rsv = rsv[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) da8xx_edma0_pdata.slave_map = da850_edma0_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) edma_pdev = platform_device_register_full(&da8xx_edma0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (IS_ERR(edma_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pr_warn("%s: Failed to register eDMA0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return PTR_ERR(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) da850_edma1_pdata.slave_map = da850_edma1_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) edma_pdev = platform_device_register_full(&da850_edma1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return PTR_ERR_OR_ZERO(edma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct resource da8xx_i2c_resources0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .start = DA8XX_I2C0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .end = DA8XX_I2C0_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct platform_device da8xx_i2c_device0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "i2c_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .resource = da8xx_i2c_resources0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct resource da8xx_i2c_resources1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .start = DA8XX_I2C1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .end = DA8XX_I2C1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_device da8xx_i2c_device1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "i2c_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .resource = da8xx_i2c_resources1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int __init da8xx_register_i2c(int instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct davinci_i2c_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (instance == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pdev = &da8xx_i2c_device0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else if (instance == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pdev = &da8xx_i2c_device1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pdev->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return platform_device_register(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct resource da8xx_watchdog_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .start = DA8XX_WDOG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .end = DA8XX_WDOG_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct platform_device da8xx_wdt_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "davinci-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .resource = da8xx_watchdog_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int __init da8xx_register_watchdog(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return platform_device_register(&da8xx_wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct resource da8xx_emac_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .start = DA8XX_EMAC_CPPI_PORT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct emac_platform_data da8xx_emac_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .version = EMAC_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct platform_device da8xx_emac_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "davinci_emac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .platform_data = &da8xx_emac_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_resources = ARRAY_SIZE(da8xx_emac_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .resource = da8xx_emac_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct resource da8xx_mdio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .start = DA8XX_EMAC_MDIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_device da8xx_mdio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "davinci_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .resource = da8xx_mdio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int __init da8xx_register_emac(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = platform_device_register(&da8xx_mdio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return platform_device_register(&da8xx_emac_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct resource da830_mcasp1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .start = DAVINCI_DA830_MCASP1_REG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* TX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* RX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct platform_device da830_mcasp1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .resource = da830_mcasp1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct resource da830_mcasp2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .start = DAVINCI_DA830_MCASP2_REG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* TX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* RX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .name = "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct platform_device da830_mcasp2_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .resource = da830_mcasp2_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct resource da850_mcasp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* TX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* RX event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .name = "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct platform_device da850_mcasp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "davinci-mcasp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .num_resources = ARRAY_SIZE(da850_mcasp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .resource = da850_mcasp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pdev = &da850_mcasp_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Valid for DA830/OMAP-L137 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!cpu_is_davinci_da830())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pdev = &da830_mcasp1_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Valid for DA830/OMAP-L137 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!cpu_is_davinci_da830())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pdev = &da830_mcasp2_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pdev->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) platform_device_register(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct resource da8xx_pruss_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .start = DA8XX_PRUSS_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .pintc_base = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct platform_device da8xx_uio_pruss_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = "pruss_uio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .resource = da8xx_pruss_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .platform_data = &da8xx_uio_pruss_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int __init da8xx_register_uio_pruss(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return platform_device_register(&da8xx_uio_pruss_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static struct lcd_ctrl_config lcd_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .panel_shade = COLOR_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .manu_name = "sharp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .controller_data = &lcd_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .type = "Sharp_LCD035Q3DG01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .manu_name = "sharp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .controller_data = &lcd_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .type = "Sharp_LK043T1DG01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct resource da8xx_lcdc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [0] = { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .start = DA8XX_LCD_CNTRL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [1] = { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct platform_device da8xx_lcdc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = "da8xx_lcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .resource = da8xx_lcdc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) da8xx_lcdc_device.dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return platform_device_register(&da8xx_lcdc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct resource da8xx_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .start = DA8XX_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .end = DA8XX_GPIO_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static struct platform_device da8xx_gpio_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .name = "davinci_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .resource = da8xx_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int __init da8xx_register_gpio(void *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) da8xx_gpio_device.dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return platform_device_register(&da8xx_gpio_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct resource da8xx_mmcsd0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .start = DA8XX_MMCSD0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static struct platform_device da8xx_mmcsd0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "da830-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .resource = da8xx_mmcsd0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) da8xx_mmcsd0_device.dev.platform_data = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return platform_device_register(&da8xx_mmcsd0_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #ifdef CONFIG_ARCH_DAVINCI_DA850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static struct resource da850_mmcsd1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .start = DA850_MMCSD1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .end = DA850_MMCSD1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static struct platform_device da850_mmcsd1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .name = "da830-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .resource = da850_mmcsd1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) da850_mmcsd1_device.dev.platform_data = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return platform_device_register(&da850_mmcsd1_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static struct resource da8xx_rproc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { /* DSP boot address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "host1cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { /* DSP interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "chipsig",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { /* DSP L2 RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .name = "l2sram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .start = DA8XX_DSP_L2_RAM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { /* DSP L1P RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .name = "l1pram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .start = DA8XX_DSP_L1P_RAM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { /* DSP L1D RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "l1dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .start = DA8XX_DSP_L1D_RAM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) { /* dsp irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static struct platform_device da8xx_dsp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .name = "davinci-rproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .resource = da8xx_rproc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static bool rproc_mem_inited __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static phys_addr_t rproc_base __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static unsigned long rproc_size __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int __init early_rproc_mem(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) char *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rproc_size = memparse(p, &endp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (*endp == '@')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rproc_base = memparse(endp + 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) early_param("rproc_mem", early_rproc_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __init da8xx_rproc_reserve_cma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct cma *cma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!rproc_base || !rproc_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) " 'nn' and 'address' must both be non-zero\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __func__, rproc_size, (unsigned long)rproc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pr_err("%s: dma_contiguous_reserve_area failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) da8xx_dsp.dev.cma_area = cma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rproc_mem_inited = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) void __init da8xx_rproc_reserve_cma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int __init da8xx_register_rproc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!rproc_mem_inited) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = platform_device_register(&da8xx_dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pr_err("%s: can't register DSP device: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct resource da8xx_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .start = DA8XX_RTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .end = DA8XX_RTC_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { /* timer irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { /* alarm irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct platform_device da8xx_rtc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .name = "da830-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .resource = da8xx_rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int da8xx_register_rtc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return platform_device_register(&da8xx_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static void __iomem *da8xx_ddr2_ctlr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) void __iomem * __init da8xx_get_mem_ctlr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (da8xx_ddr2_ctlr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return da8xx_ddr2_ctlr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!da8xx_ddr2_ctlr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pr_warn("%s: Unable to map DDR2 controller", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return da8xx_ddr2_ctlr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static struct resource da8xx_cpuidle_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .start = DA8XX_DDR2_CTL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* DA8XX devices support DDR2 power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .ddr2_pdown = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static struct platform_device da8xx_cpuidle_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .name = "cpuidle-davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .resource = da8xx_cpuidle_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .platform_data = &da8xx_cpuidle_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int __init da8xx_register_cpuidle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return platform_device_register(&da8xx_cpuidle_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct resource da8xx_spi0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .start = DA8XX_SPI0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .end = DA8XX_SPI0_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static struct resource da8xx_spi1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .start = DA830_SPI1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .end = DA830_SPI1_BASE + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .version = SPI_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .intr_line = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .dma_event_q = EVENTQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .prescaler_limit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .version = SPI_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .intr_line = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .dma_event_q = EVENTQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .prescaler_limit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static struct platform_device da8xx_spi_device[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .name = "spi_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .resource = da8xx_spi0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .platform_data = &da8xx_spi_pdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .name = "spi_davinci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .resource = da8xx_spi1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .platform_data = &da8xx_spi_pdata[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (instance < 0 || instance > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (instance == 1 && cpu_is_davinci_da850()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return platform_device_register(&da8xx_spi_device[instance]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #ifdef CONFIG_ARCH_DAVINCI_DA850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int __init da850_register_sata_refclk(int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return clk_register_clkdev(clk, "refclk", "ahci_da850");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static struct resource da850_sata_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .start = DA850_SATA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .end = DA850_SATA_BASE + 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static struct platform_device da850_sata_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .name = "ahci_da850",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .dma_mask = &da850_sata_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .num_resources = ARRAY_SIZE(da850_sata_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .resource = da850_sata_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int __init da850_register_sata(unsigned long refclkpn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = da850_register_sata_refclk(refclkpn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return platform_device_register(&da850_sata_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static struct regmap *da8xx_cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const struct regmap_config da8xx_cfgchip_config __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = "cfgchip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * This is for use on non-DT boards only. For DT boards, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * Returns: Pointer to the CFGCHIP regmap or negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct regmap * __init da8xx_get_cfgchip(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (IS_ERR_OR_NULL(da8xx_cfgchip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) da8xx_cfgchip = regmap_init_mmio(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) &da8xx_cfgchip_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return da8xx_cfgchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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