^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file contains the processor specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * of the TI DM644x, DM355, DM365, and DM646x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __DAVINCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __DAVINCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/davinci_emac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/davinci_asp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/keyscan-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/davinci/vpfe_capture.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/davinci/vpif_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/davinci/vpss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/davinci/vpbe_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/davinci/vpbe_venc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/davinci/vpbe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/davinci/vpbe_osd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAVINCI_PLL1_BASE 0x01c40800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DAVINCI_PLL2_BASE 0x01c40c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SYSMOD_VDAC_CONFIG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SYSMOD_VIDCLKCTL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SYSMOD_VPSS_CLKCTL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SYSMOD_VDD3P3VPWDN 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SYSMOD_VSCLKDIS 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYSMOD_PUPDCTL1 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* VPSS CLKCTL bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VPSS_VENCCLKEN_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VPSS_DACCLKEN_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern void __iomem *davinci_sysmod_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void davinci_map_sysmod(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAVINCI_GPIO_BASE 0x01C67000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int davinci_gpio_register(struct resource *res, int size, void *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* DM355 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ASP1_TX_EVT_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ASP1_RX_EVT_EN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* DM365 base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* DM644x base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* DM646x base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int davinci_init_wdt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* DM355 function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void dm355_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void dm355_init_time(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void dm355_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void dm355_register_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void dm355_init_spi0(unsigned chipselect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const struct spi_board_info *info, unsigned len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void dm355_init_asp1(u32 evt_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int dm355_gpio_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* DM365 function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void dm365_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void dm365_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void dm365_init_time(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void dm365_register_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void dm365_init_asp(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void dm365_init_vc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void dm365_init_ks(struct davinci_ks_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void dm365_init_rtc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void dm365_init_spi0(unsigned chipselect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const struct spi_board_info *info, unsigned len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int dm365_gpio_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* DM644x function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void dm644x_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void dm644x_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void dm644x_init_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void dm644x_init_time(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void dm644x_register_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void dm644x_init_asp(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int dm644x_gpio_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* DM646x function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void dm646x_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void dm646x_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void dm646x_register_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void dm646x_init_mcasp0(struct snd_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void dm646x_init_mcasp1(struct snd_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int dm646x_init_edma(struct edma_rsv_info *rsv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void dm646x_video_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void dm646x_setup_vpif(struct vpif_display_config *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct vpif_capture_config *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int dm646x_gpio_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern struct platform_device dm365_serial_device[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern struct platform_device dm355_serial_device[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern struct platform_device dm644x_serial_device[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) extern struct platform_device dm646x_serial_device[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif /*__DAVINCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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